Limited width parallel prefix circuits

Abstract

In this paper, we present lower and upper bounds on the size of limited width, bounded and unbounded fan-out parallel prefix circuits. The lower bounds on the sizes of such circuits are a function of the depth, width, and number of inputs. The size requirement of an N input bounded fan-out parallel prefix circuit having limited width W and extra depth k (the difference between allowed and minimum possible depth) is shown to be fl(N log2W/2 k + N) for k < log2W. This implies that insisting on minimum depth causes the circuit size to be nonlinear, while as little as log21og2W of extra depth can possibly reduce the size to linear. Also, we show that there is a clear difference between the two cases of bounded and unbounded fan-out by proving the size of a limited width, unbounded fan-out parallel prefix circuit lies between a lower bound of f~((2 + 21-k/3)N) and an upper bound of 0((2 + 21-~)N).Uniform, systolic constructions of limited width parallel prefix circuits are provided here and shown to be asymptotically optimal. By associating the width of the circuit with the number of processors and the fan-out capabilities of the circuit with the interconnection structure of a multiprocessor, time-and processor-efficient algorithms may be developed.

Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2

“…For example, as shown in Figure 6, both levels 1 and 6 of L(14) have six operation nodes, but levels 3 and 4 have only one operation node. In contrast, as already shown in Figure 5, each level of C2(14) has three or four operation nodes; this makes C2 more desirable [Carlson and Sugla 1990].…”

“…In particular, many combinational prefix circuits, which are parallel prefix algorithms on the circuit model, have been designed and studied [Brent and Kung 1982;Fich 1983;Bilgory and Gajski 1986;Snir 1986;Lakshmivarahan et al 1987;Carlson and Sugla 1990;Lakshmivarahan and Dhall 1994;Zimmermann 1997;Lin 1999;Lin and Liu 1999;Lin and Shih 1999;Lin and Chen 2003;Hinze 2004;Lin and Hsiao 2004;Lin and Su 2005;Sheeran and Parberry 2006;Zhu et al 2006;Lin and Hung 2009]. A prefix circuit of width n is represented as a directed acyclic graph containing n inputs, n outputs, at least n -1 operation nodes, and at least one duplication node.…”

“…To speed up the prefix operation, many parallel prefix algorithms for various parallel computing models have been proposed [Ladner and Fischer 1980;Kruskal et al 1985;Bilgory and Gajski 1986;Snir 1986;Lakshmivarahan et al 1987;Carlson and Sugla 1990;Lakshmivarahan and Dhall 1994;Akl 1997;Zimmermann 1997;Manohar and Tierno 1998;Lin 1999;Lin and Liu 1999;Lin and Yeh 1999;Helman and JaJa 2001;Santos 2002;Lin and Chen 2003;Lin and Yeh 2003;Datta 2004;Lin and Hsiao 2004;Lin and Su 2005;Lin 2006;Sheeran and Parberry 2006;Zhu et al 2006;Hung and Lin 2008]. In particular, many combinational prefix circuits, which are parallel prefix algorithms on the circuit model, have been designed and studied [Brent and Kung 1982;Fich 1983;Bilgory and Gajski 1986;Snir 1986;Lakshmivarahan et al 1987;Carlson and Sugla 1990;Lakshmivarahan and Dhall 1994;Zimmermann 1997;Lin 1999;Lin and Liu 1999;Lin and Shih 1999;Lin and Chen 2003;Hinze 2004;Lin and Hsiao 2004;Lin and Su 2005;…”

A new approach to constructing optimal parallel prefix circuits with small depth

“…Indeed, the prefix operation is a built-in function for parallel programming with the MPI [9]. In addition, many combinational circuits for performing the prefix operation in parallel, called parallel prefix circuits, have been designed and studied [2,4,5,8,[13][14][15]18,20,[23][24][25]31]. Many parallel prefix algorithms have also been devised [1,10,14,18,21,[26][27][28][29][30].…”

A new approach to constructing optimal prefix circuits with small depth

“…The size of a prefix circuit D , s ( D ), is the operation in parallel, called parallel prefix circuits, number of operation nodes in D, and the depth of D , have been designed and studied [2,4,5,[8][9][10][11][13][14][15][16].…”