LIMSoft: automated tool for sensitivity analysis and test vector generation

Saab, Khaled; Marche, D.; Hamida, N.B.; Kaminska, Bożena

doi:10.1049/ip-cds:19960934

Cited by 27 publications

(11 citation statements)

References 6 publications

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“…In order to reduce the required number of Monte Carlo simulations, some ( [2] and [3]) suggested evaluating circuit sensitivity and using the obtained information as guide lines to deterministically identifying the circuit corners. Once the circuit corners have been identified, the appropriate reduced number of Monte Carlo simulations for corner analysis can be executed.…”

Section: Overviewmentioning

confidence: 99%

Parametric fault simulation and test vector generation

Saab

Ben-Hamida

Kaminska

2000

Proceedings of the Conference on Design, Automation and Test in Europe

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Process variation has forever been the major fail cause of analog circuit where small deviations in component values cause large deviations in the measured output parameters. This paper presents a new approach for parametric fault simulation and test vector generation. The proposed approach utilizes the process information and the sensitivity of the circuit principal components in order to generate statistical models of the fault-free and the faulty circuit. The obtained information is then used as a measurement to quantify the testability of the circuit. This approach extended by hard fault testing has been implemented as automated tool set for IC testing called FaultMaxx and TestMaxx.

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Section: Overviewmentioning

confidence: 99%

Parametric fault simulation and test vector generation

Saab

Ben-Hamida

Kaminska

2000

Proceedings of the Conference on Design, Automation and Test in Europe

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“…Automated generation of test stimuli is the goal of the approaches outlined in [28] and [29], which employ output signal sensitivity to circuit parameters. In [28] and [29], test inputs are defined as single tone sinusoidal signals with frequency as an unknown parameter.…”

Section: A Mixed-signal Soc Testmentioning

confidence: 99%

“…The frequency at which the sensitivity of the output voltage (voltage gain) of the circuit is highest to a given component is selected to test it. Sensitivities are determined by manual analysis in [29], and by circuit simulations and the use of the adjoint network method in [28].…”

Section: A Mixed-signal Soc Testmentioning

confidence: 99%

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Test infrastructure design for mixed-signal SOCs with wrapped analog cores

Sehgal

Ozev

Chakrabarty

2006

IEEE Trans. VLSI Syst.

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Abstract-Many system-on-chips (SOCs) today contain both digital-and analog-embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results for three SOCs from the ITC '02 test benchmarks that have been augmented with three analog cores: an I-Q transmit path pair and an audio CODEC path used in cellular phone applications.

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“…Automated generation of test stimuli is the aim of approaches outlined in [12], which employ output signal sensitivity to circuit parameters. Test inputs are defined as single tone sinusoidal signals with frequency as an unknown parameter.…”

Section: Review Of Prior Workmentioning

confidence: 99%