Line Edge Roughness of Metal Lines and Time-Dependent Dielectric Breakdown Characteristics of Low-k Interconnect Dielectrics

Through silicon via impact on above BEoL Time Dependent Dielectric Breakdown

“…The robustness of low-k dielectric integration is generally assumed to be impacted by three items related to the dielectric characteristics and the topology of lines: (1) dielectric characteristics of the volume near the SiOCH / SiO 2 -TEOS interface, since trapezoidal shape of lines, due to the SiOCH etching, leads applied electrical field and resulting percolation path of dielectric breakdown to be localized close to this interface [1,2]; (2) line-to-line spacing variation, related to photolithography fluctuations [2]; (3) line edge roughness (LER), already reported as first-order reliability detractor for TDDB of low-k dielectrics [2][3].…”

“…Reliability investigations are therefore becoming critical. Besides the low-k dielectrics introduction in CMOS copper interconnects is a key point for the Back-End-of-Line reliability, since wear-out due to dielectric breakdown becomes a main concern [1][2][3]. Although 65 nm node technologies are today mature, and in high volume production, the eventual impact of Through Silicon Via (TSV) on the reliability of adjacent low-k inter metallic dielectric has to be assessed through Time Dependent Dielectric Breakdown (TDDB) analysis.…”

Interconnect Modeling: A Physical Design Perspective

“…To improve modeling accuracy, RC extraction by CMP simulator has been proposed [12]. The random component due to line edge roughness [5] is thought to be negligible because interconnect wire width or length is much larger than the size of gate poly, and the random component is averaged out. Reference [69] reports that the capacitance-extraction error of industrial state-of-theart tools is σ = 1.5%−5%.…”

“…Interconnect delay can be efficiently handled in SSTA using (5). When Elmore delay is used, deriving sensitivities to physical interconnect parameters is not very difficult; however, when model order reduction (MOR) is used for interconnectdelay analysis, which is described in Section V-A, the computational time needed for sensitivity derivation becomes a problem.…”

“…The integration of low-k dielectric and low-resistivity metals is a key factor in reducing delay and power consumption. High-accuracy critical-dimension control [2] restrains variability, and increased reliability eradicates temporal defects such as electromigration (EM) [3], stress-migration (SM) [4], and time-dependent dielectric breakdown [5]. Current lithography is supported by resolution-enhancement techniques such as optical proximity correction, subresolution assist features, offaxis illumination, and phase-shifting mask [1], [6].…”