"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs

Mercha, A.; Rafı́, J.M.; Simoen, Eddy; Augendre, E.; Claeys, Corneel

doi:10.1109/ted.2003.814983

Cited by 125 publications

(94 citation statements)

References 15 publications

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“…As soon as the gate voltage is higher than the threshold for electron valence band (EVB) tunneling a kink effect is occurring, resulting in an increase of the drain current and the appearance of a second peak in the transconductance curve. This effect has been discussed in detail and the impact of different technological parameters is well understood [15]. After an ionizing irradiation the LKE effect becomes more pronounced so that the height of the second peak increases and shifts to higher frontgate voltages as shown in Fig.…”

Section: Soi Technologiesmentioning

confidence: 93%

Physics and Modeling of Radiation Effects in Advanced CMOS Technology Nodes

Claeys

Simoen

2004

Simulation of Semiconductor Processes and Devices 2004

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The paper first describes the basic radiation-induced mechanisms such as transient effects, ionization phenomena and displacement damage. Subsequently, the impact of irradiation on advanced CMOS technology nodes is demonstrated in order to illustrate the underlying physical phenomena. Both bulk and silicon-on-insulator (SOI) technologies will be addressed. A third section discusses the present understanding and the difficulties associated with modeling of irradiation-induced device degradation. Finally, an outlook is given for some emerging semiconductor technologies such as e.g. SiGe, strained silicon, Ge and GeOI. Some aspects of cryogenic irradiations, of key importance for space applications, are also briefly mentioned.

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Section: Soi Technologiesmentioning

confidence: 93%

Physics and Modeling of Radiation Effects in Advanced CMOS Technology Nodes

Claeys

Simoen

2004

Simulation of Semiconductor Processes and Devices 2004

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“…These transistors even have augmented currents at various low voltages. Metallic element fabric to be subjected from the transient body impact that successively adds to the History impact [13,14].…”

Section: Fdsoi Devicementioning

confidence: 99%

Design Low Voltage Current Mirror at 32nm Regime

Pawar

2017

ijsrtm

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As the technology moving towards lower voltage for high stability and accurate performance. We design low voltage current mirror using IGFET, FDSOI, CNTFET.These transistor is moving towards low-voltage high-speed performance. Here in this paper, we have design low voltage current mirror for Accurate duplication of current. To obtain accurate duplication of current, we verify the performance of low voltage current mirror on FDSOI and CNTFET Transistor having the 32nm technology. The circuit is simulated with 32nm technology for FDSOI and CNTFET. They operate at lower power supply than IGFET. The simulation results show the improvement in knee voltage 1.7v and 1.3v for the current mirror. Keywords-Carbon nanotube field-effect transistor (CNTFET); Fully Depleted Silicon on Insulator (FDSOI);Insulated Gate filed effect transistor (IGFET).

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“…[9,8] the pair is then split apart, using a process that leaves a thin (relative to the thickness of the starting wafer), device-quality layer of single crystal silicon on top of the oxide layer (which has now become the BOX) on the handle wafer. This [10,11,12] is called the "layer transfer" technique, because it transfers a thin layer of device-quality silicon onto an oxide layer that was thermally grown on a handle wafer. The "layer transfer" approach has lead to the development of at least three production methods for fabrication of SOI wafers; Smart cut TM (UNIBOND) SOI wafers, Nanocleave TM SOI wafers, and ELTRANTM SOI wafers.…”

Section: Figure 1 Fabrication Process Of Soi Technologymentioning

confidence: 99%

A Theoretical Study of Low Power Soi Technology

Vandana¹

2013

(IOSR-JVSP

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"Linear kink effect" induced by electron valence band tunneling in ultrathin gate oxide bulk and SOI MOSFETs

Cited by 125 publications

References 15 publications

Physics and Modeling of Radiation Effects in Advanced CMOS Technology Nodes

Physics and Modeling of Radiation Effects in Advanced CMOS Technology Nodes

Design Low Voltage Current Mirror at 32nm Regime

A Theoretical Study of Low Power Soi Technology

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