Linearity Distortion Analysis of Junctionless Quadruple Gate MOSFETs for Analog Applications

Gupta, Santosh Kumar; Rawat, Akash; Verma, Yogesh Kumar; Mishra, Varun

doi:10.1007/s12633-018-9850-z

Cited by 38 publications

(8 citation statements)

References 17 publications

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“…To ameliorate the undesirable effects of distortion and ensure more linear behaviour, all of these quantities should have high values bar IMD3. 40,41 The formulae for the aforementioned metrics can be found in 39,40,[42][43][44][45]…”

Section: Resultsmentioning

confidence: 99%

Linearity Performance and Distortion Analysis of Carbon Nanotube Tunneling FET

Hussain

Mustakim

Saha

2021

Journal of Elec Materi

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In this research work, we have varied several parameters of a carbon nanotube based tunneling field effect transistor (CNT-TFET) such as the dielectric constant of the gate insulator (j), channel length, oxide thickness, doping level, and the nature of doping to investigate how the performance of the CNT-TFET is affected. The performance analysis has been done based on the following performance criteria: Subthreshold swing (SS), threshold voltage (V T), and on-current to off-current ratio (I on /I off). In addition, we have also analyzed how linearity and distortion figures of merit such as second-order voltage intercept point (VIP2), third-order voltage intercept point (VIP3), third-order input intercept point (IIP3), and third-order intermodulation distortion (IMD3) are affected by parametric variation. By observing the impact of parametric variation on this large number of performance metrics, a compromise choice of structural parameters is possible depending on the application. Moreover, we have proposed an asymmetric doping design that suppresses the highly undesirable ambipolar behavior in CNT-TFET. In a real-space approach, the simulation study has been carried out using the elegant non-equilibrium Green's function (NEGF) formalism considering tight-binding Hamiltonian.

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Section: Resultsmentioning

confidence: 99%

Linearity Performance and Distortion Analysis of Carbon Nanotube Tunneling FET

Hussain

Mustakim

Saha

2021

Journal of Elec Materi

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“…The impact of temperature on wireless performance is very important as the transistor needs to have lesser distortion at the output of the device. The least value of intermodulation and harmonic distortion at the outputs indicates superior linearity performance 35 . To examine the linearity performance, several figure of merits (FOMs) specifically various higher order voltage and current intercepts points (VIP2, VIP3, and IIP3), various harmonic distortion (IMD3, HD2, and HD3) and 1 dB compression point have been presented for multi‐channel FinFET structure.…”

Section: Resultsmentioning

confidence: 99%

“…They found that optimized top and bottom value of fin width (7 nm and 15 nm) provides better SCEs and RF performance. Santosh et al 35 investigates RF/linearity performance of junctionless quadruple gate MOSFET for variation of physical device parameter and desirable values are obtained for higher value of oxide thickness and for higher doping concentration.…”

Section: Introductionmentioning

confidence: 99%

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

Das

Maity

Chowdhury

et al. 2021

Int J RF Mic Comp-Aid Eng

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This dissertation demonstrates the reliability issues associated with the temperature of Ge multi‐channel fin shaped field‐effect transistor (Mch‐FinFET). Temperature dependence on short channel effectss such as threshold voltage (Vth), sub‐threshold swing (SS), and switching ratio are observed. The variation in temperature on various important radio frequency (RE)/analog, linearity, and harmonic distortion characteristics are studied and analyzed over a wide range of temperatures (300–500 K). The simulation study revealed that Mch‐FinFET devices exhibit 61.6% improvement in ION with minimum SS value. The improvement of SS, switching ratio and Vth can be observed with temperature fall. The enhancement in performance of various RF/analog attributes such transconductance, device efficiency, transconductance frequency product, gain frequency product, cut‐off frequency, and intrinsic gain with lowering of temperature. However, Mch‐FinFET device provides a significant improvement of higher‐order current and voltage intercept points such as IIP3, VIP2, VIP3, and 1 dB compression point with lesser harmonic distortion such as HD2, HD3, and THD at elevated temperature. The superior efficiency of DC and RF/analog attributes, greater linearity, and minor harmonic distortion performance of Mch‐FinFET make it more considerable to design low power Complementary metal–oxide–semiconductor (CMOS) circuits.

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“…IMD 3 is the third order intermodulation distortion, which represents the extrapolated current at which the first and third intermodulation harmonic currents are equal specified in equation (9). Non-linearity and distortion metrics evaluated are expressed below [29]:…”

Section: Non-linearity and Distortion Analysismentioning

confidence: 99%

Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

Ansari,

Jha,

Sharma

et al. 2023

Eng. Res. Express

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This article proposes four Triple Gate (TG) FinFET structures with variations in fin height and fin width with 22 nm gate length on SOI substrate. The four different structures are presented in terms of (fin height, fin width) such as D1(20 nm, 22 nm), D2(10 nm and 20 nm), D3(8 nm and 18 nm), and D4(6 nm and 16 nm). The objective is to investigate the effect of fin dimensions on the DC characteristics of the FinFET structures. Upon analyzing the DC characteristics, it is observed that D1 had an order of leakage current of 10−10 A, while D4 had 10−14 A. Additionally, D1 and D4 exhibited a change in subthreshold swing (SS) of 30%, with D1 having a value of 78.1 mV/decade and D4 having 60.0 mV/decade. The RF metric gate-to-gate capacitance reduced from D1 to D4 by 90%, and the threshold voltage of D4 was found to be 0.342 V. Based on these findings, D4 structure had better optimized results. Furthermore, temperature is varied on the D4 structure from 300 K to 500 K; electrical, RF, and distortion parameters were analyzed thoroughly. It is observed that the RF parameters reduced while the temperature increased, with transconductance frequency product (TFP), gain frequency product (GFP), and cut-off frequency (fT) decreasing by 92.1%, 98.5%, and 92.4%, respectively. However, the distortion parameters slightly increased with an increase in temperature. VIP2, VIP3, gm2, gm3, and IMD3 decreased, indicating that the device performance in wireless applications increases with increasing temperature. Overall, findings suggest that the D4 (6 nm and 16 nm) structure is a promising candidate for wireless applications, especially those that require high-temperature operation.

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Linearity Distortion Analysis of Junctionless Quadruple Gate MOSFETs for Analog Applications

Cited by 38 publications

References 17 publications

Linearity Performance and Distortion Analysis of Carbon Nanotube Tunneling FET

Linearity Performance and Distortion Analysis of Carbon Nanotube Tunneling FET

Impact of temperature on radio frequency/linearity and harmonic distortion characteristics of Ge multi‐channel fin shaped field‐effect transistor

Temperature analysis of TG FinFET on electrical, RF and distortion parameters for wireless applications

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