LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture

Tradowsky, Carsten; Thoma, Florian; Hübner, Michael; Becker, Jürgen

doi:10.1109/sies.2012.6356596

Cited by 5 publications

(2 citation statements)

References 19 publications

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“…Architecture-centric languages like MIMOLA [16] capture the structure of the processor. Mixed languages that bring together the two processor aspects have also been proposed [22], [28]. Thanks to high level processor descriptions, it becomes possible to make high level analysis of processor behaviors.…”

Section: Methodsmentioning

confidence: 99%

Hardware architecture specification and constraint-based WCET computation

Herbegue

Cassé

Filali

et al. 2013

2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)

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The analysis of the worst-case execution times is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis for these systems must be performed on binary code and based on static analysis. OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files to describe the microarchitecture. The latter information is usually inadequate to describe real architectures and, therefore, requires specific modifications, currently performed by hand, to allow correct time calculation. In this paper, we propose to extend Sim-nML in order to support the description of modern microarchitecture features along the instruction set description and to seamlessly derive the time calculation. This time computation is specified as a constraint solving problem that is automatically synthesized from the extended Sim-nML. Thanks to its declarative aspect, this approach makes easier and modular the description of complex features of microprocessors while maintaining a sound process to compute times.

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Section: Methodsmentioning

confidence: 99%

Hardware architecture specification and constraint-based WCET computation

Herbegue

Cassé

Filali

et al. 2013

2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)

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“…The i-Core is an adaptive, reconfigurable application-specific processor that is able to exploit the novel paradigm of invasive computing described in [9]. The micro architecture of the i-Core is built using the same high-level ADL approach that will be used in the SmartLoCore concept as well [10].…”

Section: B Application-specific Instruction-set Processors (Asip) Anmentioning

confidence: 99%

SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor

Tradowsky

Gädeke

Bruckschlogl

et al. 2014

2014 22nd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

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During the last decades, a great shift to processing on mobile and ubiquitous devices has been taken place. With this movement also the integration of different sensors, especially inertial sensors, has gained strong interest. One approach is to combine inertial sensors with other localization systems. However, this needs real-time processing capabilities and low power consumption, which is usually a problem when performing this task on the main processor with the operating system on top. In this paper, we present an adaptive localization processor called SmartLoCore including an intuitive development flow that allows hardware/software co-design trade-offs during design-time. These options include running the algorithm in software, adding new additional instructions to the core instruction-set and offloading complex mathematics onto dedicated hardware. We show the applicability with a complex localization application example and highlight the benefits of the proposed concept. We conclude that the SmartLoCore concept shows a very promising potential for a large variety of mobile systems.

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