Lithography induced layout variations in 6-T SRAM cells

Abstract

A simulation study of lithography induced layout variations in 6-T SRAM cells is presented. Lithography simulations of a complete 6-T SRAM cell layout, including active n+/p+ regions layer and poly-gate layer were performed. The smallest feature size was assumed to be 45 nm. 76 positions of the projector focus were simulated for each layer in total. TCAD simulations of 32nm single gate FD SOI MOSFETs were performed to calculate the electrical behavior. SPICE parameters were extracted from reference results obtained by TCAD simulations. More than 5000 variations of the the static and dynamic SRAM cell performance in dependence on lithography induced variations of the physical transistor width and the physical gate length were simulated

A New High Speed Low Power Dissipation Three-Element Si-Based SRAM Cell

“…As the forward bias was increased above V bf , the diode got into the low resistance branch. The low resistance branch is at μA/μm 2 level, in practical application, the diode area can be scaled to 50 nm×50 nm [8], at this area range, I 1 would be at nA/Cell level, which will cause a low power dissipation (compared with the static power consumption that exists in all cells in conservation state, the dynamic power consumption only exists in one cell within each write cycle, therefor, the dynamic power dissipation can be ignored).…”