Localized Micro-Inserts Connection for Smart Card Secure Micro Packaging

Brun, J.J.; Franiatte, R.; Puget, C.; Souriau, Jean-Charles; Mathieu, L.; Ponthenier, G.; Sillon, N.; Bonvalot, B.; Depoutot, F.; Barbe, S.

doi:10.1109/hdp.2005.251415

Cited by 4 publications

(3 citation statements)

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“…This 2D connection structure has been tested and evaluated in a previous work [4]. It has been shown that an electrical efficiency of more than 90% can be achieved.…”

Section: ) From 2d To 3d Integrationmentioning

confidence: 94%

“…Among these approaches, the most conventional use fusible bumps which, once soldered to the pad, enable connection between dies. The LETI has over the last few years developed a technology implementing µbumps located (figures 1 and 2) on the connection pads [3,4]. These small spikes are Nickel-base and are formed at the interconnection point between the two circuits by a combination of lithography and electrolytic plating.…”

Section: ) From 2d To 3d Integrationmentioning

confidence: 99%

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3D via belt technology

Brun

Boutry

Franiatte

et al. 2009

2009 59th Electronic Components and Technology Conference

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Three-dimensional die stacking with vertical interconnections through Si dies is potentially the best semiconductor system integration technique. With its incredibly promising improvements in speed and power dissipation in IC's, it has attracted increased attention in recent times. But this approach needs to perform through silicon vias at wafer level step and such wafers are not always available.This paper presents a 3D solution for interconnection of a base wafer with standard dies. Firstly, it consists in manufacturing copper pillars dedicated to vertical connection and manufactured around flip-chip position by electroplating. Then dies are connected to the substrate face-down by µ-insert technology. In order to obtain a new surface, the wafer is embedded in a polymer and planarized by grinding enabling copper pillars to be connected. A new rerouting and interconnection system enables a second die hybridization. This report presents the first manufacturing approaches and electrical results. IntroductionPortable products such as cell phones, hearing aids, digital cameras and so on require system miniaturization and a high interconnection level to meet the demand for increased functionality in less overall space. But over the last few years, the compactness of these devices has become such that the cost of the packaging is preponderant compared with the price of silicon and of testing. It is therefore of paramount importance that approaches such as wafer level packaging (WLP) be found in order to execute the steps collectively. This technique in fact consists in assembling and connecting individual dies provided by different manufacturers using steps that are compatible with existing microtechnology methods.Different 3D architectures have emerged to reduce the packaging size [1,2]. Several approaches are proposed by companies and laboratories and each of them presents specific advantages and drawbacks. The first results of one of these technologies developed at the LETI are given here.

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“…This 2D connection structure has been tested and evaluated in a previous work [4]. It has been shown that an electrical efficiency of more than 90% can be achieved.…”

Section: ) From 2d To 3d Integrationmentioning

confidence: 94%

Section: ) From 2d To 3d Integrationmentioning

confidence: 99%

3D via belt technology

Brun

Boutry

Franiatte

et al. 2009

2009 59th Electronic Components and Technology Conference

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“…The combination of multi wavelengths OCT and NIR microscopy has been used to control a die to wafer stacking process. Figure 14 shows results obtained on a test vehicle using micro-inserts for interconnection 6 . A Kelvin bump pattern which includes a matrix of 16 micro-inserts has been used for electrical resistance measurement 7 .…”

Section: Die Stackingmentioning

confidence: 99%

Optical Characterization and Defect inspection for 3D stacked IC technology

Fresquet¹,

Piel²

2014

International Symposium on Microelectronics

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Advanced packaging technologies are rapidly evolving and 3D architectures requires new inspection and metrology techniques. Existing techniques need to be improved but new techniques must be developed to address new challenges induced by the last fabrication processes. To increase the development speed, it is a big advantage that metrology and defect inspection need to be present on the same platform and a flexible tool, with multi sensors, to be more versatile facing the different step of the process will be presented in this paper As 3D IC devices utilize TSVs for direct interconnect, the depth, top and bottom CD (critical diameter) of such TSVs with a diameter as small as 5 μm with a high aspect ratio is characterized. During wafer temporary bounding, which is an handling technique that allows wafer thinning with a thickness of less than 100 μm, by selecting the most sensitive sensor, determination of the thickness of each layer of the stack could be determined at the same time: silicon substrate, thin glue layer of few microns only and carrier which could be silicon or glass. After back-side processing and wafer thinning, the determination of the remaining silicon thickness (RST) below the TSV could be determined. Moreover back side roughness after grinding is also determined. After wafer thinning process, the TSVs are revealed at the back side of the wafer, leaving to appear copper pillars. The pillars height and co-planarity measurements are then addressed. Post CMP process control will be addressed by full field interferometry especially prior Copper to Copper direct bonding. Concerning the defect inspection, the NIR microscopy is used to control die to wafer stacking process, to reveal voids in the glue and cracks on the grinded silicon substrate. In this paper, we will present fast and nondestructive optical sensors based on low coherence infrared and white light interferometry and spectrometry techniques. These different sensors mounted on the same tool allow characterizing specifically and with an excellent sensitivity the different process steps described above. Concerning the defect inspections, techniques based on infrared microscopy and images techniques processing will be detailed and results will be presented to illustrate the possibilities of this inspection by microscopy.

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