Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub-$\mu$  A Sensing Resolution, and 17.5-nS Read Access Time

Shih, Yu-Jen; Lee, Chia-Fu; Chang, Yu-Hao; Lee, Po-Hao; Lin, Hon-Jarn; Chen, Yulin; Lin, Ku-Feng; Yeh, Ta‐Chuan; Yu, Hung-Chang; Chuang, Harry; Chih, Yu-Der; Chang, Jonathan

doi:10.1109/jssc.2018.2889106

Cited by 33 publications

(3 citation statements)

References 6 publications

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“…Spin-transfer torque (STT)-MRAM demonstrates excellent endurance, retention, fast access speed, and low power switching characteristics [1][2][3]. It has been used in last-level cache [4][5], embedded systems [6][7][8], microcontroller unit (MCU) [9] and so on. Non-volatile magnetic RAM (MRAM) design shows high yield requirement due to sub-28-nm CMOS process and sub-100-nm magnetic tunnel junction (MTJ) device applied to hybrid integration [10].…”

Section: Introductionmentioning

confidence: 99%

CSME: A novel cycle-sensing margin enhancement scheme for high yield STT-MRAM

Cai

Liu

Zhou

et al. 2020

Microelectronics Reliability

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Section: Introductionmentioning

confidence: 99%

CSME: A novel cycle-sensing margin enhancement scheme for high yield STT-MRAM

Cai

Liu

Zhou

et al. 2020

Microelectronics Reliability

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“…Spin Torque Magnetoresistive Random Access Memory (ST-MRAM) is currently emerging as a leading technology for embedded memory in microcontroller units [1]- [3], as well as for standalone memory [4]. ST-MRAM indeed provides a compact fast and non volatile memory, which is fully embeddable in modern CMOS, and features outstanding endurance.…”

Section: Introductionmentioning

confidence: 99%

“…However, a major challenge of RRAMs and ST-MRAMs is the presence of bit errors. In the case of ST-MRAM, this issue is traditionally solved by using ECC [1]- [3] or special programming strategies [28]. In this work, we look at the possibility to use ST-MRAMs directly to store the binarized synaptic weights, without relying on any of these techniques.…”

Section: Introductionmentioning

confidence: 99%

Implementing Binarized Neural Networks with Magnetoresistive RAM without Error Correction

Hirtzlin¹,

Penkovsky²,

Klein³

et al. 2019

Preprint

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One of the most exciting applications of Spin Torque Magnetoresistive Random Access Memory (ST-MRAM) is the inmemory implementation of deep neural networks, which could allow improving the energy efficiency of Artificial Intelligence by orders of magnitude with regards to its implementation on computers and graphics cards. In particular, ST-MRAM could be ideal for implementing Binarized Neural Networks (BNNs), a type of deep neural networks discovered in 2016, which can achieve state-of-the-art performance with a highly reduced memory footprint with regards to conventional artificial intelligence approaches. The challenge of ST-MRAM, however, is that it is prone to write errors and usually requires the use of error correction. In this work, we show that these bit errors can be tolerated by BNNs to an outstanding level, based on examples of image recognition tasks (MNIST, CIFAR-10 and ImageNet): bit error rates of ST-MRAM up to 0.1% have little impact on recognition accuracy. The requirements for ST-MRAM are therefore considerably relaxed for BNNs with regards to traditional applications. By consequence, we show that for BNNs, ST-MRAMs can be programmed with weak (low-energy) programming conditions, without error correcting codes. We show that this result can allow the use of low energy and low area ST-MRAM cells, and show that the energy savings at the system level can reach a factor two.

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