LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Ghezzo, M.; Kaminsky, E.B.; Nissan-Cohen, Y.; Frank, Peter; Saia, R.

doi:10.1149/1.2097120

Cited by 26 publications

(3 citation statements)

References 16 publications

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“…This technique was applied to integrated circuit processing at the end of 1980 1,2 for the measurement of stress induced by local oxidation of silicon ͑LOCOS͒ 3 in the Si substrate. After these first reports, the technique rapidly found its way into the semiconductor research centers and microelectronics industry for stress measurements near nitride and oxide stripes, LOCOS and alternative LOCOS such as polybuffered local oxidation of silicon ͑PBLOCOS or LOPOS͒ 4 and polysilicon encapsulated local oxidation ͑PELOX͒, 5 deep and shallow trenches, near metal and silicide lines, in silicon-germanium ͑Si-Ge͒ films and even in microelectromechanical systems ͑MEMS͒ and complete Si chips. [6][7][8][9] Although the technique is relatively simple and offers fast qualitative information on a͒ Now with LIMMS/CNRS-IIS, Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505 Japan; electronic mail: vsenez@iis.u-tokyo.ac.jp b͒ local stress, it has two partial drawbacks.…”

Section: Introductionmentioning

confidence: 99%

Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Raman spectroscopy

Senez

Armigliato

Wolf

et al. 2003

Journal of Applied Physics

100

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Articles you may be interested inConvergent beam electron diffraction measurements of relaxation in strained silicon using higher order Laue zone line splitting J. Appl. Phys. 105, 063526 (2009); 10.1063/1.3093693 Convergent beam electron diffraction investigation of strain induced by Ti self-aligned silicides in shallow trench Si isolation structures J. Appl. Phys. 99, 064504 (2006); 10.1063/1.2179136 Strain analysis in silicon substrates under uniaxial and biaxial stress by convergent beam electron diffraction J. Vac. Sci. Technol. B 23, 940 (2005); 10.1116/1.1924583Determining the relationship between local lattice strain and slip systems of dislocations around shallow trench isolation by convergent-beam electron diffraction Test structures consisting of shallow trench isolation ͑STI͒ structures are fabricated using advanced silicon ͑Si͒ technology. Different process parameters and geometrical features are implemented to investigate the residual mechanical stress in the structures. A technology computer aided design homemade tool, IMPACT, is upgraded and optimized to yield strain fields in deep submicron complementary metal-oxide-semiconductor devices. Residual strain in the silicon substrate is measured with micro-Raman spectroscopy ͑-RS͒ and/or convergent beam electron diffraction ͑CBED͒ for large ͑25 m͒ and medium size ͑2 m͒, while only CBED is used for deep submicron STI ͑0.22 m͒. We propose a methodology combining CBED and technology computer aided design ͑TCAD͒ with -RS to assess the accuracy of the CBED measurements and TCAD calculations on the widest structures. The method is extended to measure ͑by CBED͒ and calculate ͑by TCAD͒ the strain tensor in the smallest structures, out of the reach of the -RS technique. The capability of determining, by both measurement and calculation, the strain field distribution in the active regions of deep submicron devices is demonstrated. In particular, it is found that for these structures an elastoplastic model for Si relaxation must be assumed.

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Section: Introductionmentioning

confidence: 99%

Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Raman spectroscopy

Senez

Armigliato

Wolf

et al. 2003

Journal of Applied Physics

100

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“…give a better bird's beak than conventional LOCOS with minimal thermal budget was ideal. temperatures and for a shorter period of time compared to conventional LOCOS, as the pad oxide for PBL is much thinner than for conventional LOCOS [21].…”

Section: Figure 2-21 -Silo and Locos Structures Before And After Fielmentioning

confidence: 99%

“…Founded on the results presented in [7] and [21], PBL was implemented in the process designed for this thesis. Minimizing the thermal budget and thus minimizing the boron suck-out is a key objective.…”

Section: Poly-buffered Locos (Pbl) Compared To Conventional Locosmentioning

confidence: 99%

Minimizing nMOS Edge Leakage in Fully Depleted Silicon-on-Insulator CMOS Using Poly-Buffered LOCOS Isolation

Trifoli¹

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A process has been designed, implemented and tested to minimize edge-leakage effects in fully depleted silicon-on-insulator (FD SOI) nMOSFET (nMOS) devices encountered in previous student project SOI CMOS fabrication runs in the Carleton University Microfabrication Laboratory. A layout with test arrays, including enclosed geometry transistors, was designed to perform a test fabrication run. The process uses optimized oxidation steps and Poly-Buffered LOCal Oxidation of Silicon (PBL) isolation with minimal mask steps and fabrication time. The fabricated test transistors revealed that some subthreshold edge leakage was still present in the nMOS devices. SEM imaging showed that the field oxide had been almost entirely unintentionally etched away during processing. This reduction in the field oxide thickness creates parasitic edge transistors. Sentaurus simulations imply that if not for this field oxide loss, the fabricated nMOS devices would have had minimal leakage with no kink in the subthreshold curve.

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Etching Processes in Semiconductor Manufacturing

Donohoe

Turner²,

Jackson

2013

Materials Science and Technology

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The sections in this article are Introduction Wet Etching Dry Etching Etch Control and Metrology Equipment: Description of Hardware Wet Sinks Dry Processing Etch Hardware Barrel Etchers Plasma Etchers Reactive Ion Etchers Remote Plasma Generation: Microwave and ECR Endpoint, Diagnostic and Control Techniques Endpoint Monitors Optical Emission Spectroscopy ( OES ) Laser Interferometry Residual Gas Analysis/Mass Spectroscopy RF and Bias Voltage Diagnostic Tools/Metrology for Process Control Machine Related Metrology Process Related Measurements Control Techniques Present Control Strategy What is Needed? Possible Solutions Process Discussion: General Considerations Isolation Gate Definition Silicides Contact Etching Planarization Etch Steps Via Etching Metal Etching Etch Processing for 4 Mb DRAM Wafer Preparation 6.5.2 N‐Well P‐Well Field Implant Iso Mask Connector Mask Trench Capacitor Inter‐Polysilicon Oxide Mask Gate Mask LDD Spacer Etch Contact Etch Poly 3 Polycide Etch Contact Mask 2 Metal 1 Mask Pad Mask/Polyimide Mask Summary

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LOPOS: Advanced Device Isolation for a 0.8 μm CMOS/BULK Process Technology

Cited by 26 publications

References 16 publications

Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Raman spectroscopy

Strain determination in silicon microstructures by combined convergent beam electron diffraction, process simulation, and micro-Raman spectroscopy

Minimizing nMOS Edge Leakage in Fully Depleted Silicon-on-Insulator CMOS Using Poly-Buffered LOCOS Isolation

Etching Processes in Semiconductor Manufacturing

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