Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes

Gentile,; Rovini,; Fanucci,

doi:10.1109/dsd.2007.4341494

Cited by 19 publications

(7 citation statements)

References 13 publications

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“…Partially parallel decoding architecture is a good trade-off between hardware complexity and decoding throughput and it is best accomplished by Layered Decoding (LD) schedule [19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37]. In this schedule the rows of PCM are divided into several layers, and each iteration of the BP algorithm is likewise split into several sub-iterations, each running over one layer of the PCM.…”

Section: The Distinctive Characteristics Of Ldpc Codes Such As Their mentioning

confidence: 99%

A Modified Shuffling Method to Reduce Decoding Complexity of QC-LDPC Codes

Hasani¹,

Lopacinski²,

Kraemer³

2020

Preprint

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Layered decoding (LD) of Low-Density Parity-Check (LDPC) codes is a decoding schedule that facilitates partially parallel architectures for performing Belief Propagation (BP)-based iterative algorithms. It has reduced implementation complexity and memory overhead compared to fully parallel architectures and higher convergence speed compared to both serial and parallel architectures. In this paper, we introduce a modified form of shuffling of the Parity-Check Matrices (PCMs) of Quasi-Cyclic LDPC (QC-LDPC) codes, which is basically an interleaving operation of the rows of the PCM. The modified shuffling method just like the conventional shuffling method results in a PCM in which each layer can be produced by the circulation of its above layer one symbol to the right. However, it additionally guarantees the weights of the columns in each layer to be either zero or one. Then, we show that due to these two properties, the number of occupied Look-Up Tables (LUTs) on a Field Programmable Gate Array (FPGA) is reduced by about 93% and consumed on-chip power by nearly 80%. Nevertheless, shuffling doesn’t degrade Bit Error Rate (BER) performance compared with the non-shuffled case. Additionally, decoding throughput is not sacrificed for low SNR values and its degradation is negligible until the BER of 1e-6.

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Section: The Distinctive Characteristics Of Ldpc Codes Such As Their mentioning

confidence: 99%

A Modified Shuffling Method to Reduce Decoding Complexity of QC-LDPC Codes

Hasani¹,

Lopacinski²,

Kraemer³

2020

Preprint

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“…(iii) Multiply the value of previous item values with a normalized factor α and set δ i,j,k to be the result as (13).…”

Section: Check-node Processormentioning

confidence: 99%

“…In this paper, we introduce a fix base matrix H as Fig. 10 shows, this matrix is introduced in IEEE 802.16e [13]. The proposed encoder and decoder have been implemented on an Xilinx Kintex UltraScale XCKU040FFVA1156-2-E FPGA which provides 242 400 look-up tables (LUTs), 484 800 flip-flops (FF) and 600 block RAMs (BRAMs).…”

Section: Implementation and Performance Based On Fpgamentioning

confidence: 99%

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Implementation of encoder and decoder for LDPC codes based on FPGA

Cheng

Shen

Liao

et al. 2019

Journal of Systems Engineering and Electronics

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This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check (IR-QC-LDPC) codes, with a dual-diagonal parity structure. A normalized min-sum algorithm (NMSA) is employed for decoding. The whole verification of the encoding and decoding algorithm is simulated with Matlab, and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6% and 1.04%. Based on the results of simulation, multi-code rates are compatible with different basis matrices. Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array (FPGA). The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6% are realized based on FPGA.

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“…Researchers proposed some forwarding scheme [6][7][8][9] in order to improve the performance of relay systems. Considering the detrimental wireless fading effects, packets cannot always be decoded correctly, literature [6] proposes a new hybrid AF and DF scheme with network coding for TWRN, where the relay node can amplify and forward the network coded information when one of the packets from the two source nodes cannot be correctly decoded.…”

Section: Introductionmentioning

confidence: 99%

Product-Decode-Forward Scheme for Two-way Relay Networks

Sang¹,

Xu²,

Deng³

et al. 2016

dtetr

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In this paper, we propose a new efficient Product-Decode-Forward (PDF) scheme for two-way relay networks, where two source nodes communicate with each other with the help of relay nodes. In the proposed scheme, the relay node only performs decoding once on the product of received signals from two sources and broadcasts to source nodes. The scheme can improve the performance of the two-way relay networks and has less decoding complexity compared with DF scheme. Theoretical and simulation results show that the proposed PDF scheme can provide better (bit error rate) BER performance and achieve more channel capacity compared with Product-Forward (PF) scheme.

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Low-Complexity Architectures of a Decoder for IEEE 802.16e LDPC Codes

Cited by 19 publications

References 13 publications

A Modified Shuffling Method to Reduce Decoding Complexity of QC-LDPC Codes

A Modified Shuffling Method to Reduce Decoding Complexity of QC-LDPC Codes

Implementation of encoder and decoder for LDPC codes based on FPGA

Product-Decode-Forward Scheme for Two-way Relay Networks

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