Low complexity hardware interleaver for MIMO-OFDM based wireless LAN

Asghar, Rizwan; Liu, Dake

doi:10.1109/iscas.2009.5118113

Cited by 9 publications

(12 citation statements)

References 8 publications

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“…We use Matlab to simulate the LDPC interleaving formula. First assume that the input sequence is [0, 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19] and the modulation order is 4. e corresponding figure of this sequence is shown in Figure 7.…”

Section: Verification Of Interleaved Address Formula For Datamentioning

confidence: 99%

“…en, the identical hardware structure is reused by careful comparison to reduce the cost of silicon for multistandards [12]. Although these works cover 2G, 3G, and even 4G standards [13], the latest 5G standard has not been studied in them. erefore, with respect to the 5G NR standard 3GPP TS 38.212 [14], this paper proposes a scheme of hardware reuse and cost-saving for polar-encoded channel interleaver [15] and LDPC-encoded channel interleaver [16].…”

Section: Introductionmentioning

confidence: 99%

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Hardware Sharing for Channel Interleavers in 5G NR Standard

Xiong

Dai

et al. 2021

Security and Communication Networks

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Interleaver module is an important part of modern mobile communication system. It plays an important role in reducing bit error rate and improving transmission efficiency over fading channels. In 5G NR (5th Generation New Radio) standards, LDPC (low-density parity-check) and polar channel codes are employed for data channels and control channels, respectively. If multiple interleavers are implemented separately for them, the cost increases significantly. To address this issue, a hardware multiplexing scheme for channel interleavers based on LDPC and polar codes is proposed in this paper. Firstly, the formulas for the processes of the control channel interleaving and data channel interleaving are derived with respect to 5G NR standard. Then, the hardware implementation structures of the two interleavers are given. Subsequently, hardware reuse is proposed by sharing the similar or identical parts between the two hardware structures. Simulation results verify the correctness of our proposed scheme and demonstrate that it can realize the hardware sharing of the two kinds of channel interleavers to reduce the cost of silicon.

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Section: Verification Of Interleaved Address Formula For Datamentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hardware Sharing for Channel Interleavers in 5G NR Standard

Xiong

Dai

et al. 2021

Security and Communication Networks

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“…The work in [19][20][21][22] covers the DVB-related interleaver implementations. Literature [23][24][25][26][27] focuses on more than one interleaver implementations with reconfigurability for multiple variants of wireless LAN 27]. These techniques require multiple-stream processing in parallel, thus requiring parallel addresses generation and memory architecture as shown in Figure 1.…”

Section: Previous Workmentioning

confidence: 99%

“…The two recursive terms mentioned in (26) and (27) are easy to implement in hardware ( Figure 13) with the help of a LUT to provide the starting values for g (x) and f 2 .…”

Section: Turbo Code Interleaving In 3gpp-lte and Wimaxmentioning

confidence: 99%

Multimode Flex-Interleaver Core for Baseband Processor Platform

Asghar

Liu

2010

Journal of Computer Systems, Networks, and Communications

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This paper presents a flexible interleaver architecture supporting multiple standards like WLAN, WiMAX, HSPA+, 3GPP-LTE, and DVB. Algorithmic level optimizations like 2D transformation and realization of recursive computation are applied, which appear to be the key to reach to an efficient hardware multiplexing among different interleaver implementations. The presented hardware enables the mapping of vital types of interleavers including multiple block interleavers and convolutional interleaver onto a single architecture. By exploiting the hardware reuse methodology the silicon cost is reduced, and it consumes 0.126 mm 2 area in total in 65 nm CMOS process for a fully reconfigurable architecture. It can operate at a frequency of 166 MHz, providing a maximum throughput up to 664 Mbps for a multistream system and 166 Mbps for single stream communication systems, respectively. One of the vital requirements for multimode operation is the fast switching between different standards, which is supported by this hardware with minimal cycle cost overheads. Maximum flexibility and fast switchability among multiple standards during run time makes the proposed architecture a right choice for the radio baseband processing platform.

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“…Upadhyaya et al have tested an address generating circuit on FPGA for WiMAX multimode interleaver/deinterleaver in [14,15] and WLAN multimode interleaver in [16] for all permissible code rates and modulation schemes based on FSM. Asghar, et al [17], proposed a twofold interleaver architecture for different spatial stream application in 802.11n. Zhang et al [18] had presented, a low complexity architecture for interleaver/ deinterleaver suitable for MIMO application in 802.11a/g/n wireless LAN.…”

Section: Introductionmentioning

confidence: 99%

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

Venkatachalam¹,

Lakshminarayanan²,

Sellathurai³

2016

IET Computers & Digital Techniques

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Developing a reconfigurable transceiver to support multiple protocols seamlessly and efficiently is an extremely tough task. Wireless standards such as wireless local area network (IEEE 802.11a/g) and WiMAX (IEEE 802.16e) incorporate block interleaving technique to overcome the occurrence of burst errors during transmission. Field Programmable Gate Array (FPGA) implementation of floor and modulus (MOD) functions to perform the two step permutation for attaining the new index is quite complex. In this study, the authors propose a low complexity and area efficient reconfigurable architecture for multimode interleaver address generator to support multiple wireless standards. In addition, a novel MOD_row and MOD_column circuit are proposed to compute MOD function for row and column counter values, respectively. The proposed address generation circuitry supports BPSK, QPSK, 16-QAM and 64-QAM modulation schemes under all possible code rates. The reconfigurable address generator for various block size and modulation scheme are implemented on Xilinx Spartan XC3S400 FPGA and the functionalities are verified through simulation. The synthesis results of the proposed design shows a reduction of 60% in resource utilisation and an improvement of 46% in operating frequency over the existing approaches.

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Low complexity hardware interleaver for MIMO-OFDM based wireless LAN

Cited by 9 publications

References 8 publications

Hardware Sharing for Channel Interleavers in 5G NR Standard

Hardware Sharing for Channel Interleavers in 5G NR Standard

Multimode Flex-Interleaver Core for Baseband Processor Platform

Low complexity and area efficient reconfigurable multimode interleaver address generator for multistandard radios

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