Low complexity transform competition for HEVC

IEEE Trans. Consumer Electron.

Philippe

Fezza

et al. 2022

Self Cite

The H.266/versatile video coding (VVC) standard is the most recent ITU/ISO video coding standard finalized in July 2020. VVC includes several new coding tools at different levels of the coding scheme. These coding tools enable a significant bitrate saving of up to 50% for the same subjective video quality than its predecessor H.265/high efficiency video coding (HEVC). Among these tools, we can cite the multiple transform selection (MTS) which selects at the encoder horizontal and vertical transforms among three trigonometrical transforms, including discrete cosine transform (DCT) type II, discrete sine transform (DST) type VII and DCT type VIII. Unlike the DCT-II, the DST-VII does not have efficient fast algorithmic implementation. Moreover, the MTS increases the memory usage required to store the coefficients of the three transforms. Consequently, this paper targets an efficient approximation of the DST-VII kernel based on the DCT-II and adjustment stage. The approximation of the DST-VII is modeled as an integer optimization problem jointly minimizing the error and the orthogonality of the approximate DST-VII under sparsity constraint of the adjustment stage. The sparse nonlinear optimizer (SNOPT) solver with an additional relaxation constraint is used to solve the problem and find the best sparse adjustment band matrices for different transform sizes. The DCT-VIII is then computed from the approximate DST-VII with pre/post processing operations involving only sign changes and input/output reordering. The proposed approximation provides a significant reduction in both arithmetic operations and memory usage. Moreover, it preserves the coding gain brought by the MTS under the VVC reference software. These advantages make our solution suitable for energy-efficient hardware H.266//VVC encoders and decoders deployed on consumer electronic devices.

Section: ) Transforms For Video Compressionmentioning

confidence: 99%

Hardware-Friendly Multiple Transform Selection Module for the VVC Standard

IEEE Trans. Consumer Electron.

Philippe

Fezza

et al. 2022

Self Cite

“…The concept of separable transforms competition has been widely investigated for HEVC [17], [18] which considers only DCT-II along with DST-VII for Intra luma blocks of size 4×4 [19], and then integrated in the JEM software [10]. This latter enables five trigonometrical transform types including DCT-II, V and VIII, and DST-I and VII.…”

Section: A Multiple Transform Selection In Vvcmentioning

confidence: 99%

Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard

Kammoun

IEEE Trans. Circuits Syst. Video Technol.

Philippe

et al. 2020

Self Cite

The future video coding standard named Versatile Video Coding (VVC) is expected by the end of 2020. VVC will enable better coding efficiency than the current High Efficiency Video Coding (HEVC) standard. This coding gain is brought by several coding tools. The Multiple Transform Selection (MTS) is one of the key coding tools that have been introduced in VVC. The MTS concept relies on three transform types including Discrete Cosine Transform (DCT)-II, Discrete Sine Transform (DST)-VII and DCT-VIII. Unlike the DCT-II that has fast computing algorithms, the DST-VII and DCT-VIII rely on more complex matrix multiplication. In this paper an approximation approach is proposed to reduce the computational cost of the DST-VII and DCT-VIII. The approximation consists in applying adjustment stages, based on sparse block-band matrices, to a variant of DCT-II family mainly DCT-II and its inverse. Genetic algorithm is used to derive the optimal coefficients of the adjustment matrices. Moreover, an efficient hardware implementation of the forward and inverse approximate transform module is proposed. The architecture design includes a pipelined and reconfigurable forward-inverse DCT-II core transform as it is the main core for DST-VII and DCT-VIII computations. The proposed 32-point 1D architecture including low cost adjustment stages allows the processing of a video in 2K and 4K resolutions at 1095 and 273 frames per second, respectively. A unified 2D implementation of forwardinverse DCT-II, approximate DST-VII and DCT-VIII is also presented. The synthesis results show that the design is able to sustain a video in 2K and 4K resolutions at 386 and 96 frames per second, respectively, while using only 12% of Alms, 22% of registers and 30% of DSP blocks of the Arria10 SoC platform.

“…block of residuals). The transform competition has been investigated under HEVC standard [16], [17], and more recently under the Joint Exploration Model (JEM) software [18]. The JEM codec defines five trigonometrical transform types including DCT-II, V and VIII, and DST-I and VII.…”

Section: A Separable Transform Modulementioning

confidence: 99%

“…The total memory size is 17408-bits which corresponds to 68 columns of 256 bit-depth (256×68). The ROM stores the coefficients of the 64-point DCT-II, 32-point, 16-point, 8-point and 4-point DST-VII matrix coefficients. The 64-point DCT-II is decomposed using its butterfly structure, and the resultant sub-matrices are stored.…”

Section: A Hardware Separable Transform Modulementioning

confidence: 99%

Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Farhat

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

Grill

et al. 2020

Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational complexity. This rises a need to design an efficient and optimised implementation especially for embedded platforms with limited memory and logic resources. One of the newly introduced tools in VVC is the Multiple Transform Selection (MTS). This latter involves three Discrete Cosine Transform (DCT)/Discrete Sine Transform (DST) types with larger and rectangular transform blocks. In this paper, an efficient hardware implementation of all DCT/DST transform types and sizes is proposed. The proposed design uses 32 multipliers in a pipelined architecture which targets an ASIC platform. It consists in a multi-standard architecture that supports the transform block of recent MPEG standards including AVC, HEVC and VVC. The architecture is optimized and removes unnecessary complexities found in other proposed architectures by using regular multipliers instead of multiple constant multipliers. The synthesized results show that the proposed method which sustain a constant throughput of two pixels/cycle and constant latency for all block sizes can reach an operational frequency of 600 Mhz enabling to decode in real-time 4K videos at 48 fps.