Low computational complexity hardware implementation of Laplacian Pyramid

Zeinolabedin, Seyed Mohammad Ali; Karimi, Nader; Samavi, Shadrokh

doi:10.1109/iraniancee.2010.5507025

Cited by 6 publications

(9 citation statements)

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“…The proposed LP structure of Zeinolabedin [28] addresses the main issues in the conventional hardware implementation of LP [1,8,20,25,26]. Two important tools, polyphase decomposition and noble identities [23], are employed in the proposed structure.…”

Section: Proposed Laplacian Pyramid (Lp) Structurementioning

confidence: 99%

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Structuring of Contourlet Transform for Pipeline-Based Implementation

Zeinolabedin

Karimi

Samavi

et al. 2015

Circuits Syst Signal Process

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Contourlet transform (CT) is a powerful image processing tool. Even though many promising applications have been proposed, no hardware implementation of CT has been reported. This paper analyzes CT to form a structure which is hardware implementable. CT consists of two main parts, Laplacian pyramid (LP) and directional filter bank (DFB). In both parts, novel algorithmic changes are proposed for realizing efficient hardware architecture. In the proposed LP structure, 50 % of the arithmetic operations have been reduced and it operates twice as fast as the existing implementations. To the best of our knowledge, DFB has not comprehensively been studied for hardware implementation so far. Thus, we first analyze DFB to figure out its hardware-oriented structure and then propose DFB architecture. Finally, analysis and simulation results demonstrate that the proposed CT architecture achieves the realtime performance (40 frame/s) operating at 76 MHz which is verified through FPGA implementation. Moreover, since all stages utilize fixed-point arithmetic operations, B SeyedCircuits Syst Signal Process the comprehensive quantization analysis is performed to keep the MSE and PSNR values in an acceptable range.

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Section: Proposed Laplacian Pyramid (Lp) Structurementioning

confidence: 99%

“…Then, a sufficient number of data are stored in the FIFO in stage 6. Finally, in stage 7 the vertical convolution is performed and the high-frequency coefficients of two neighboring rows are obtained [28].…”

Section: Lp Architecturementioning

confidence: 99%

Structuring of Contourlet Transform for Pipeline-Based Implementation

Zeinolabedin

Karimi

Samavi

et al. 2015

Circuits Syst Signal Process

Self Cite

View full text Add to dashboard Cite

show abstract

“…The size of the FIFO significantly affects the total area and power of the design. For instance, FIFOs consume more than 75% of the route area and power in [19] and more than 80% of power consumption in [20]. So in order to reach the ultra-low power design, the memory usage should be exactly investigated to figure out how we can improve the power and area without degrading the operating frequency and output accuracy.…”

Section: Ultra-low Power Digital Image Processors Design Challengesmentioning

confidence: 99%

“…Rapid advancement in VLSI systems has enabled the real-time hardware implementation of high computational complexity image/video processing algorithms. Some recent works requiring fast hardware implementation are video codec [3], computational photography [2], wavelet transform [31], laplacian pyramid [20] and biomedical applications [1]. Early image/video processors focused on improving the speed/throughput of the systems while the contemporary state-of-the-art image/video processors confront additional challenges such as low power consumption and real-time processing.…”

Section: Introductionmentioning

confidence: 99%