Low-cost sequential ATPG with clock-control DFT

Abrarnovici, M.; Yu, Xiaoming; Rudnick, E.M.

doi:10.1109/dac.2002.1012629

Cited by 9 publications

(1 citation statement)

References 24 publications

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“…Both scan [1], [2] and nonscan [3]- [8] DFT techniques have been proposed. The popularity of full (or almost full) scan results from the following advantages.…”

Section: Introductionmentioning

confidence: 99%

Autoscan: a scan design without external scan inputs or outputs

Pomeranz

Reddy

2005

IEEE Trans. VLSI Syst.

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We propose a design-for-testability technique for synchronous sequential circuits called autoscan. Autoscan uses scan chains similar to conventional scan. However, it gives up the external scan inputs and outputs in order to eliminate the test data volume associated with them. Scan operations under autoscan improve the circuit testability by allowing the circuit state to be modified through shifting. Due to the removal of the scan inputs and outputs, synthesis of scan chains under autoscan does not have to satisfy all the constraints imposed on conventional scan chains. We describe a synthesis procedure for autoscan chains, and demonstrate that autoscan allows us to detect almost all the faults that are detectable using conventional scan. We use random sequences in order to show that sequential test generation is not necessary under autoscan. We also describe a test generation procedure, and discuss the effect of autoscan on fault diagnosis.

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“…Both scan [1], [2] and nonscan [3]- [8] DFT techniques have been proposed. The popularity of full (or almost full) scan results from the following advantages.…”

Section: Introductionmentioning

confidence: 99%

Autoscan: a scan design without external scan inputs or outputs

Pomeranz

Reddy

2005

IEEE Trans. VLSI Syst.

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ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box

Li,

Orailoglu

2023

2023 IEEE 32nd Asian Test Symposium (ATS)

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On application of output masking to undetectable faults in synchronous sequential circuits with Design-For-Testability logic

Pomeranz

Reddy

2003

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

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Design-for-testability (DFT ) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. One way to deal with such faults is to mask (or ignore) their fault effects when they appear on the circuit outputs, without masking the detection of faults that need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of other masked faults.

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Low-cost sequential ATPG with clock-control DFT

Cited by 9 publications

References 24 publications

Autoscan: a scan design without external scan inputs or outputs

Autoscan: a scan design without external scan inputs or outputs

ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box

On application of output masking to undetectable faults in synchronous sequential circuits with Design-For-Testability logic

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