Low-cost wafer bumping

Abstract

As the demand for flip-chip interconnects mounts across an increasingly large spectrum of products and technologies, several wafer-bumping processes have been developed to produce the small solder features required for this interconnect technology. These processes differ significantly in complexity and commensurate cost. Recently, a new bumping process developed at IBM Research called injection-molded solder, or IMS, has shown the capability to combine low-cost attributes with high-end capabilities. The development of IMS technology was driven by the need to reduce wafer-bumping costs while simultaneously addressing the conflicting needs of increasing wafer dimensions to 300 mm, decreasing bump and pitch dimensions below 75 lm on 150-lm centers, and optimal Pb-free alloy selection and processing. This paper describes IMS technology for both standard eutectic SnPb and Pb-free wafer bumping. Existing mainstream bumping technologies are also reviewed, with a focus on the challenges of new industry requirements. Early manufacturing challenges are addressed, including solutions that demonstrated the appropriateness of IMS technology for low-cost 300-mm Pb and Pb-free wafer bumping. Early process and reliability data are also reviewed.

Microelectronic Packaging Trends and the Role of Nanotechnology

“…This technology, which is known as C4NP (C4-new process) was developed [19] at IBM and is now commercialized by Suss MicroTec [22,23]. C4NP is a solder transfer technology where molten solder is injected into prefabricated and reusable glass templates (molds).…”

Critical Factors Affecting the Undercooling of Pb-free, Flip-Chip Solder Bumps and In-situ Observation of Solidification Process

“…A schematic diagram showing the DSC sample preparation process with a Si chip containing several hundred flip-chip-size solder bumps. Two types of flip-chip-size solder samples were prepared by using the low cost C4NP (Controlled Collapse Chip Connection: New Process) wafer bumping process [10]. The first type was on Si chips where flip-chip-size solder bumps were deposited on Cu/Ni UBM (100 pim pad size on 200 pim pitch); and the second type was on a glass mold with tiny etched cavities ( 100 pim in diameter), which were filled with solders by the C4NP wafer bumping process.…”

‘Effects of Minor Alloying Additions on the Properties and Reliability of Pb‐Free Solders and Joints’

“…Controlling the undercooling of Sn-rich solders is an important issue in such a new waferbumping process, C4NP (C4 new process), where melting/solidification of multiple solder bumps in a small volume is a key metallurgical process involved [33,39]. In C4NP, a molten solder is filled into a glass mold containing prefabricated cavities of I/O footprint of a silicon wafer, and then solder bumps are transferred from the glass mold to the wafer by aligning/ melting the solidified bumps.…”

“…These new findings have also closely related with the reliability issues of Sn-rich solder joints. To name a few items, such as excessive Cu consumption [26], easy fatigue crack growth along large Ag 3 Sn plates [16], chip-joining issues due to large undercooling [33], void formation and drop impact failure [22][23][24], crystal-orientation effects on thermal fatigue [28] and electromigration [34], and others.…”