Low frequency noise and radiation response in the partially depleted SOI MOSFETs with ion implanted buried oxide

Abstract

Low frequency noise behaviors of partially depleted silicon-on-insulator (PDSOI) n-channel metal-oxide semiconductors (MOS) transistors with and without ion implantation into the buried oxide are investigated in this paper. Owing to ion implantation-induced electron traps in the buried oxide and back interface states, back gate threshold voltage increases from 44.48 V to 51.47 V and sub-threshold swing increases from 2.47 V/dec to 3.37 V/dec, while electron field effect mobility decreases from 475.44 cm2/V·s to 363.65 cm2/V·s. In addition, the magnitude of normalized low frequency noise also greatly increases, which indicates that the intrinsic electronic performances are degenerated after ion implantation processing. According to carrier number fluctuation theory, the extracted flat-band voltage noise power spectral densities in the PDSOI devices with and without ion implantation are equal to 7×10−10 V2·Hz−1 and 2.7×10−8 V2·Hz−1, respectively, while the extracted average trap density in the buried oxide increases from 1.42×1017 cm−3·eV−1 to 6.16×1018 cm−3·eV−1. Based on carrier mobility fluctuation theory, the extracted average Hooge’s parameter in these devices increases from 3.92×10−5 to 1.34×10−2 after ion implantation processing. Finally, radiation responses in the PDSOI devices are investigated. Owing to radiation-induced positive buried oxide trapped charges, back gate threshold voltage decreases with the increase of the total dose. After radiation reaches up to a total dose of 1 M·rad(si), the shifts of back gate threshold voltage in the SOI devices with and without ion implantation are −10.82 V and −31.84 V, respectively. The low frequency noise behaviors in these devices before and after radiation are also compared and discussed.

Total Ionizing Dose Radiation Effects in the P-Type Polycrystalline Silicon Thin Film Transistors

“…Thus the band gap range (∆𝜑 p ) over which the interface traps contribute to the shift of threshold voltage is about ∆𝜑 p ≈ 𝜑 SI − 𝜑 WI ≈ 𝜑 f . [16] Therefore, the variation of interface trap densities (∆𝑁 it = 𝜑 f ∆𝐷 it , per unit area) can be then estimated, [17,18] as graphed in Fig. 3.…”

“…where 𝜇 0 is the mobility prior to irradiation, 𝜂 is a fitting parameter which is about 6.56 × 10 −13 cm 2 in this work. The variation of threshold voltage results from the formation of interface traps and oxide trapped charges 018501-2 (𝑁 ox ), which can be calculated by [18,20]…”

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

“…Third, the lowfrequency noise in MOS transistors is higher than the noise in BJTs, as one can see in Figure 15. In this figure, the data are for 134 nMOS transistors from [22,47,48,49,50,51,72,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123], and for 53 pMOS transistors from [47,52,86,…”

“…Input-referred voltage noise S V G (gate voltage 1/f noise at 1Hz) in silicon MOS transistors compared to the corresponding S V B in silicon npn BJTs. ( ) for nMOS transistors from[22,47,48,49,50,51,72,82,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123], ( ) for pMOS transistors from[47,52,…”

Metastable Electron Traps in Modified Silicon-on-Insulator Wafer

“…Due to the instable state of these shallow electron traps, electrons can tunnel 056101-2 into or out of them easily after applying bias to the substrate terminal, thus leading to the hysteretic phenomenon in the back-gate 𝐼-𝑉 curve. [10][11][12]18] Figure 4 shows the forward and backward sweep back-gate transfer 𝐼-𝑉 curves of control and modified SOI devices. It is interesting that modified wafers A and B show the 𝐼-𝑉 curve hysteretic phenomenon, whereas the modified wafer C and the control one do not.…”