Low input impedance current comparator using in pulse-width modulation

Lin, Chun Wei; Lin, Sheng Feng

doi:10.1109/icce.2010.5670696

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…Designs [6] [7] [8] had come up with high speed circuits , but when compared to proposed one those consume more power and slow in response. In 2010 author [9] had come up with a new approach a low input impedance current comparator using pulse width modulation. Circuit [9] pre-occupied with more number of MOS and Capacitors than any of the designs.…”

Section: Introductionmentioning

confidence: 99%

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High Speed Average Power CMOS Current Comparator

Thrivikramaru

Baghel

2012

2012 International Conference on Communication Systems and Network Technologies

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This work proposes the new CMOS Current Comparator circuit suitable for High Speed and Marginal Power applications. Proposed circuit had been simulated in a proprietary 180 nm CMOS process, using Cadence Spectre Simulator and UMC models. Current comparator circuit had impressed with current pulses ranging from Milli-Amperes to Nano-Amperes and its Speed and Power consumption had been simulated and measured. When made a comparison with the earlier reported circuits, our circuit achieves Very High Speed of operation and acceptable power consumption. For Micron range input currents the power consumption of the newly proposed current comparator is very much lower than the other earlier proposed circuits.

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Section: Introductionmentioning

confidence: 99%

“…In 2010 author [9] had come up with a new approach a low input impedance current comparator using pulse width modulation. Circuit [9] pre-occupied with more number of MOS and Capacitors than any of the designs. In this paper we are comparing the results obtained by the proposed design with earlier published papers [6] and [8].…”

Section: Introductionmentioning

confidence: 99%

High Speed Average Power CMOS Current Comparator

Thrivikramaru

Baghel

2012

2012 International Conference on Communication Systems and Network Technologies

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High Speed Low Power CMOS Current Comparator

Thrivikramaru

Baghel

2012

2012 International Conference on Communication Systems and Network Technologies

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Balanced low input impedances CMOS current comparator

Lin

2012

IEICE Electron. Express

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This paper presents a continuous-time current comparator with low input impedance enhancing the accuracy of comparison. The proposed circuit employs low impedance common-gate structures as input stages and further uses common-source feedback structures to enable extremely reduction of input impedances. The input impedances are well designed to be balanced, so that the proposed design can be applied to perform precise comparison between two terminals with tiny varied currents. An implemented chip was fabricated by TSMC 0.35 µm CMOS process with its input impedances and propagation delay are 66.8 Ω, 66.6 Ω and 2.5 ns respectively while the average power consumption is about 1.64 mW.

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Low input impedance current comparator using in pulse-width modulation

Cited by 3 publications

References 7 publications

High Speed Average Power CMOS Current Comparator

High Speed Average Power CMOS Current Comparator

High Speed Low Power CMOS Current Comparator

Balanced low input impedances CMOS current comparator

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