Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers

Digital-to-Frequency Converters With a DTC: Theoretical Analysis of the Output SFDR

“…In a DPC ( Fig. 1a), the control of the output period is accomplished by adding a continuously incremented delay to the edges of a fixed reference clock [29]- [33]. The most recent versions of DPCs, like the one shown in Fig.…”

“…Recent research in DTCs for low-power fractional PLLs [41]- [43] has led to substantial improvements in DTC performance and has boosted the development of high-speed implementations at GHz frequencies that are suitable for use in DDS systems [25], [26], [29]. Most of these DTCs exploit a constant-slope delay generation [44] and achieve more than 10−bit resolution, a few LSB INL and a FoM down to a few fJ/conversion.…”

“…The increase of 6 dB/octave of the worst-case spur with F CW is still valid in the presence of INL. The approximation of the maximum spur in (29) can be applied for every INL pattern, the shape factor being determined by E Ĩ NL , that can be calculated as shown in Appendix C.…”

“…DTCs for spur correction have been proposed inside DPC systems [15], [27]- [29], while in this paper we introduce a DTC in a DFC architecture, targeting 50 % duty-cycle pulseoutput. We will analyze the DTC specifications (resolution, linearity) that impact the output-spectrum purity and derive simple equations to predict the maximum spurs, to facilitate the system design.…”

“…Whatever the delay mechanism of the DTC is, e.g. constant-slope charging of a capacitor starting from a variable start voltage[25],[26], variable current charging[37],[47],[48] or a variable capacitive load[29], all DTCs can be characterized by their number of bits, INL and full-scale delay, as used inFig. 7.…”