Low-Overhead FPGA Middleware for Application Portability and Productivity

Abstract

Reconfigurable computing devices such as field-programmable gate arrays (FPGAs) offer advantages over fixed-logic CPU and GPU architectures, including improved performance, superior power efficiency, and reconfigurability. The challenge of FPGA application development, however, has limited their acceptance in high-performance computing and high-performance embedded computing applications. FPGA development carries similar difficulties to hardware design, requiring that developers iterate through register-transfer level designs with cycle-level accuracy. Furthermore, the lack of hardware and software standards between FPGA platforms limits productivity and application portability, and makes porting applications between heterogeneous platforms a time-consuming and often challenging process. Recent efforts to improve FPGA productivity using high-level synthesis tools and languages show promise, but platform support remains limited and typically is left as a challenge for developers. To address these issues, we present RC Middleware (RCMW), a novel middleware that improves productivity and enables application and tool portability by abstracting away platform-specific details. RCMW provides an application-centric development environment, exposing only the resources and standardized interfaces required by an application, independent of the underlying platform. We demonstrate the portability and productivity benefits of RCMW using four heterogeneous platforms from three vendors. Our results indicate that RCMW enables application productivity and improves developer productivity, and that these benefits are achieved with less than 7% performance and 3% area overhead on average.

Compiler-driven FPGA virtualization with SYNERGY

“…Primitives for FPGAs include sharing FPGA fabric [9,14,26,50,51,93], spatial multiplexing [15,28,84,91], context switch [59,77], memory virtualization [1,18,62,96], relocation [40], preemption [60], and interleaved hardware-software task execution [8,30,84,91]. Core techniques include virtualizing FPGA fabric, including regions [71], tasks [73], processing elements [21], IPC-like communication primitives [66], and abstraction layers/overlays [7,33,48,49,85] Extending OS abstractions to FPGAs is an area of active research. ReconOS [62] extends eCos [22] with hardware threads similar to Hthreads [70].…”

“…FPGA compilation can be further improved with a virtualization layer. Overlay-based virtualization [7,42,48,49,52,95] abstracts away target-specific details and enables fast compilation and lower deployment latency. The approach reduces utilization and performance.…”

Chimera

“…On the developer side, in order to tackle the lack of systematic support for FPGA use and make them more appealing to work with, new software paradigms/architectures have been investigated and proposed. One proposition is a low-overhead FPGA middleware of Kirchgessner et al [26]. They presented a middleware called RCMW that improves and enables application and tool portability.…”

AvA: Accelerated Virtualization of Accelerators

“…Table 6 shows prior GPU virtualization and trade-offs across virtualization properties (see §2). FPGA virtualization has a long history [31,34,48,57,58,69,74,77,88]. Most prior work relies on hardware-specific features, focuses on sharing in a single protection domain [55], or virtualization primitives [83].…”