Low‐power 25.4–33.5 GHz programmable multi‐modulus frequency divider

Abstract

A 25.4-33.5 GHz wideband CMOS programmable multi-modulus divider with low power consumption is demonstrated. For a high operating frequency and low power consumption, a direct injection-locked frequency divider is used as the prescaler and followed directly by a dual-modulus divided-by-8/9 divider without any driving circuits. The dynamic-loading CML D flip-flips are utilised in the dualmodulus divider which further reduces the power consumption. Implemented in a 90 nm CMOS process, a frequency division from 542 to 654 in steps of 2 is achieved. Measurements show that the self-resonant frequency of the divider is 14.76 GHz, and the locking range is from 25.4 to 33.5 GHz for the total frequency division ratio at an input power of 0 dBm. The power consumption for the maximum division ratio and 0 dBm input power is 15.48 mW at a supply voltage of 1.2 V. The total chip size is 0.72 × 0.47 mm.

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“…The divide-by-2/3 divider cells are implemented in differential cascade voltage switch logic (DCVSL) [7,8] for saving the power consumption. The multi-modulus divider provides a division ratio as in expression (6).…”