The balance compensating techniques for asymmetric Marchand balun are presented in this letter. The amplitude and phase difference are characterized explicitly by and , from which the factors responsible for the balance compensating are determined. Finally, two asymmetric Marchand baluns, which have normal and enhanced balance compensation, respectively, are designed and fabricated in a 0.18 CMOS technology for demonstration. The simulation and measurement results show that the proposed balance compensating techniques are valid in a very wide frequency range up to millimeter-wave (MMW) band.

A 30-50 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with a flat high power gain (S 21), along with a flat low-noise figure (NF) is demonstrated for the Atacama large millimetre array (ALMA) band-1 (31.3-45 GHz) system applications. The high S 21 and low NF are achieved because the triple-well transistors are utilised with their respective source and body terminals connected together. Furthermore, the bandwidth extension and gain flatness is achieved due to the careful design of the inductive-peaking networks. The LNA has a measured S 21 of 21.5 ± 1.5 dB, a minimum NF (NF min) of 3.8 dB at 32.5 GHz, an average NF (NF avg) of 4.67 dB over the range of 30-50 GHz and an input third-order intercept point (IIP3) of 0 dBm, with a DC power consumption of 20.4 mW at 1.2 V supply. The proposed LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain bandwidth product and highest IIP3 suitable for the ALMA band-1 system applications.

A 26–47.9 GHz ultrawideband CMOS dual injection‐locked frequency divider (dual‐ILFD) with high input impedance is demonstrated. As the differential input signal is injected into the gate of the PMOS tail transistor and NMOS switch transistor, the proposed divider has high input impedance and can be driven easily by the preceding driving circuits. Meanwhile, the locking range of the proposed divider is extended significantly by fully utilizing the dual‐injection technique. The proposed dual‐ILFD is fabricated in a standard 90‐nm CMOS process and on‐wafer measurements are performed. The measurements show that the free‐running frequency of the divider is 19.11 GHz. At an incident power of 0 dBm, a total locking range from 26 to 47.9 GHz is achieved. The power consumption is 2.88 mW at a supply voltage of 1.2 V. The total chip size is 0.62 × 0.42 mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2126–2129, 2014

A 25.4-33.5 GHz wideband CMOS programmable multi-modulus divider with low power consumption is demonstrated. For a high operating frequency and low power consumption, a direct injection-locked frequency divider is used as the prescaler and followed directly by a dual-modulus divided-by-8/9 divider without any driving circuits. The dynamic-loading CML D flip-flips are utilised in the dualmodulus divider which further reduces the power consumption. Implemented in a 90 nm CMOS process, a frequency division from 542 to 654 in steps of 2 is achieved. Measurements show that the self-resonant frequency of the divider is 14.76 GHz, and the locking range is from 25.4 to 33.5 GHz for the total frequency division ratio at an input power of 0 dBm. The power consumption for the maximum division ratio and 0 dBm input power is 15.48 mW at a supply voltage of 1.2 V. The total chip size is 0.72 × 0.47 mm.

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