Low Power and Area Efficient Carry Select Adder

Kumar, Vaibhav; Raj, Pani Prithvi; Lakshminarayanan, G.; Sellathurai, Mathini

doi:10.1166/jolpe.2014.1352

Cited by 34 publications

(67 citation statements)

References 6 publications

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“…The architecture of carry select adder with D-latch consists of five groups of different bit size RCA and D-Latch. In this method, only one adder is used to reduce the area, power consumption and delay when compared to regular Carry Select Adder (CSLA) [16]. Each of the two additions is performed in one clock cycle.…”

Section: Multiplier Less Normal Modementioning

confidence: 99%

Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing

Padmapriya¹,

Prabha²

2015

Microprocessors and Microsystems

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Section: Multiplier Less Normal Modementioning

confidence: 99%

Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing

Padmapriya¹,

Prabha²

2015

Microprocessors and Microsystems

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“…In [1] Vedic multiplier is implemented using BEC based carry select adder. There is scope to use more efficient carry select adder instead of BEC based CSLA [2]. Hence new Vedic multiplier is proposed using more efficient carry select adder.…”

Section: The 4 X 4 Vedic Multiplication Block Diagram Is Shown Inmentioning

confidence: 99%

“…Xilinx tool is used for the simulation. First of all, BEC based CSLA [2] and modified CSLA [3] are designed for 8-16-32 bit widths in Xilinx schematic entry tool. Results for these two CSLAs are shown in Table I.…”

Section: B Modified Cslamentioning

confidence: 99%

Design of Vedic-multiplier using area-efficient Carry Select Adder

Gokhale¹,

Bahirgonde²

2015

2015 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

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In this paper, area-efficient Vedic multiplier is designed using modified Carry Select Adder (CSLA). As the multiplication is nothing but subsequent addition process, adder is important block in the design of multiplier. Simple Ripple Carry adder (RCA) can be used for implementing multiplier. Digital adder has problem of carry propagation, thus carry select adder is used instead. Carry select adder is known to be one of the fastest adder structures. Here novel technique that is Vedic multiplier is implemented instead of normal multipliers like add and shift multiplier, array multiplier etc. Here multiplier is designed based on ancient Vedic multiplication technique. The goal of this paper is to design area-efficient Vedic multiplier based on crosswise and vertical algorithms. Conventional CSLA designs are compared with proposed design to prove its efficiency. On an average, modified CSLA has 29 % less area than Binary to Excess one Converter (BEC) based CSLA for different bit widths. Proposed Vedic multiplier is designed using modified CSLA, which has approximately 10 % less area than BEC based Vedic multiplier. It shows improved performance in terms of area. Proposed design is also compared with the Booth multiplier. Proposed multiplier showed more excellent results than Booth multiplier.

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“…To overcome the above mentioned issues, the authors [21] carried out the gate level optimization for a 1-bit CSLA structure by exploring the redundancy in the sum and carry generation boolean expression. Hence, the need of EX-OR gate for generating the half sum in the conventional approach has been eliminated at each bit level.…”

Section: B Modified Carry Select Addermentioning

confidence: 99%

“…In this paper, we discuss the implementation of FIR filter using novel MAC unit realized with the modified carry select adder proposed in [21]. The performance of 5-tap and 9-tap FIR Filter are compared in terms of area, delay and power using the conventional MAC and modified MAC.…”

Section: Introductionmentioning

confidence: 99%

Design of area and power efficient digital FIR filter using modified MAC unit

Kumar¹,

Nalluri²,

Lakshminarayanan³

2015

2015 2nd International Conference on Electronics and Communication Systems (ICECS)

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A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift and add logic. Most of the DSP applications demand faster adders for its arithmetic computations. Carry Select Adder (CSLA) is a well known adder for its faster computation time. Recently, an efficient Carry Select Adder (CSLA) was proposed which significantly reduce the area and power by eliminating the redundant logic gates at each bit level. In this paper, we propose an area and power efficient FIR filter implementation using modified Multiply and Accumulate (MAC) unit. The performance analysis of the proposed FIR filter is estimated with the MAC unit realized by the conventional adder and the modified carry select adder as well. The proposed FIR filter architecture with length of 5-tap and 9-tap are developed using Verilog HDL and implemented using SAED 90nm CMOS technology. The ASIC synthesis results show that the Area Delay Product(ADP) of the proposed 5-tap and 9-tap filter gains an improvement of 18.26% and 13.94%, respectively over the conventional method. Similarly, the Power Delay Product(PDP) is improved by 16.80% and 12.54%, respectively.

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Low Power and Area Efficient Carry Select Adder

Cited by 34 publications

References 6 publications

Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing

Design of an efficient dual mode reconfigurable FIR filter architecture in speech signal processing

Design of Vedic-multiplier using area-efficient Carry Select Adder

Design of area and power efficient digital FIR filter using modified MAC unit

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