Low power and fast DCT architecture using multiplier-less method

Aakif, M. El; Belkouch, Saïd; Chabini, Noureddine; Hassani, Moha M’Rabet

doi:10.1109/ftfc.2011.5948920

Cited by 15 publications

(15 citation statements)

References 19 publications

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“…This algorithm requires a uniform scaling factor of

\sqrt{2} / 4

at the end of each output value to obtain the original 1D-DCT. However, the scaling factor is included in both DCT and IDCT so there will be no effect on the result of compression or in any other applications [25, 26]. …”

Section: Methodsmentioning

confidence: 99%

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Siddiqui

Reza

Kanesan

et al. 2014

The Scientific World Journal

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A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and area while maintaining high speed and accuracy in DCT applications. The proposed design combines the techniques of Canonical Signed Digit (CSD) representation and CSE to implement the multiplier-less method for fixed constant multiplication of DCT coefficients. Furthermore, symmetry in the DCT coefficient matrix is used with CSE to further decrease the number of arithmetic operations. This architecture needs a single-port memory to feed the inputs instead of multiport memory, which leads to reduction of the hardware cost and area. From the analysis of experimental results and performance comparisons, it is observed that the proposed scheme uses minimum logic utilizing mere 340 slices and 22 adders. Moreover, this design meets the real time constraints of different video/image coders and peak-signal-to-noise-ratio (PSNR) requirements. Furthermore, the proposed technique has significant advantages over recent well-known methods along with accuracy in terms of power reduction, silicon area usage, and maximum operating frequency by 41%, 15%, and 15%, respectively.

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“…This algorithm requires a uniform scaling factor of

\sqrt{2} / 4

Section: Methodsmentioning

confidence: 99%

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Siddiqui

Reza

Kanesan

et al. 2014

The Scientific World Journal

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show abstract

“…When employing , the annotation (x,y) refers to a fixed-point wordlength of x+y-bits where x and y represent the number of bits of the integer and fractional parts, respectively. Results of DCTA implementation using (12,8), (12,4) and (12, 2)-bit wordlengths are shown in this section. In comparison, DCTM represents coefficients calculated using Matlab code that implements the 3-D DCT, and represents a Matlab implementation of the inverse 3-D DCT.…”

Section: Test Bench and Rate Distortion Performancementioning

confidence: 99%

“…The presented architectures produce very good image quality using all the selected wordlengths. The average PSNR of the eight test sequences for SPDFA are ∞, 57 and 45 dB using (12,8), (12,4) and (12, 2)-bit wordlengths, respectively. DPDFA achieves very comparable results.…”

Section: Test Bench and Rate Distortion Performancementioning

confidence: 99%

“…Transforms such as the Fourier Transform (FT) [1][2][3][4][5], Wavelet Transform (WT) [6][7][8][9], and Cosine Transform (CT) [10][11][12][13][14] play a critical part in various Digital Signal Processing (DSP) applications, including audio, image and video systems. Much of the usefulness of these transforms arises from their frequency and time-frequency representations and properties including the decorrelation property, energy compactness, and the availability of fast algorithms for their computation.…”

Section: Introductionmentioning

confidence: 99%

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New fast and area-efficient pipeline 3-D DCT architectures

Al-Azawi

Nibouche²,

Boussakta

et al. 2019

Digital Signal Processing

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The efficient implementation of 3-D transforms is a challenging task due to the computation complexity, memory and area requirements of such transforms. One important 3-D transform is the 3-D Discrete Cosine Transform (3-D DCT) used in many image and video processing systems. In this paper, two new pipeline architectures for the 3-D DCT computation using the 3-D DCT Vector-Radix algorithm (3-D DCT VR) are presented. These architectures are scalable and parameterisable with regards to different wordlengths and pipelining levels. Their arithmetic component requirements are reduced to the order of ( 2 ) in contrast with ( ) for 3-D DCT architectures in the literature, while at the same time they can keep similar or better area-time complexity.

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“…Read-only memory (ROM) free 1-D DCT architecture was discussed in [8], and this architecture is based on DA method with reduced area and power reduction. As in [9], an unsigned constant coefficient multiplication was done by moving two negative signs to the next adder to make them positive, and it was implemented using multiplier-less operation. The prime Nlength DCT was divided into similar cyclic convolution structures, and the DCT was implemented using systolic array structure [10].…”

Section: Introductionmentioning

confidence: 99%

Implementation of computation-reduced DCT using a novel method

Senthilkumar

Kunaraj²,

Seshasayanan

2015

J Image Video Proc.

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The discrete cosine transform (DCT) performs a very important role in the application of lossy compression for representing the pixel values of an image using lesser number of coefficients. Recently, many algorithms have been devised to compute DCT. In the initial stage of image compression, the image is generally subdivided into smaller subblocks, and these subblocks are converted into DCT coefficients. In this paper, we present a novel DCT architecture that reduces the power consumption by decreasing the computational complexity based on the correlation between two successive rows. The unwanted forward DCT computations in each 8 × 8 sub-image are eliminated, thereby making a significant reduction of forward DCT computation for the whole image. This algorithm is verified with various high-and less-correlated images, and the result shows that image quality is not much affected when only the most significant 4 bits per pixel are considered for row comparison. The proposed architecture is synthesized using Cadence SoC Encounter® with TSMC 180 nm standard cell library. This architecture consumes 1.257 mW power instead of 8.027 mW when the pixels of two rows have very less difference. The experimental result shows that the proposed DCT architecture reduces the average power consumption by 50.02 % and the total processing time by 61.4 % for high-correlated images. For less-correlated images, the reduction in power consumption and the total processing time is 23.63 and 35 %, respectively.

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Low power and fast DCT architecture using multiplier-less method

Cited by 15 publications

References 19 publications

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

New fast and area-efficient pipeline 3-D DCT architectures

Implementation of computation-reduced DCT using a novel method

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