Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application

Lin, Jhih-Min; Chang, Soon-Jyh; Chiu, Chin‐Fong; Tsai, Hann-Huei; Wang, Jiann-Jong

doi:10.1109/jsen.2009.2033198

Cited by 20 publications

(9 citation statements)

References 13 publications

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“…Operating at a 2.8 MHz sampling rate, with a 1V P-P range, it consumes 0.73 mW at 0.18 lm CMOS technology. Table 3 shows the comparison of the proposed ADC with those of previous works with more than 10-bit resolutions and process technologies [14], [15], [20], and [21]. The design of ADC [14] is same as the present work with a single boosted preset scheme.…”

Section: Measurement Resultsmentioning

confidence: 99%

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

Woo

Kim

2014

Analog Integr Circ Sig Process

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In this paper, we propose a comparator-based switched-capacitor (CBSC) architecture using a multi-level input tracking preset voltage scheme. The CBSC is used to compensate for technology scaling and to reduce the power consumption of a 2.8 MS/s 10-bit cyclic analog-to-digital converter (ADC). A multi-level preset voltage tracks the input voltage in order to improve the conversion rate without consuming additional power. Additionally, a comparator, current sources, and a feedback capacitor are shared to reduce the power and area of this cyclic ADC. Near the Nyquist-rate, a prototype implemented in 0.18 lm CMOS technology has a signal-to-noise and distortion ratio of 53.69 dB and a spurious-free dynamic-range of 62.36 dB, while consuming 0.73 mW of power.

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Section: Measurement Resultsmentioning

confidence: 99%

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

Woo

Kim

2014

Analog Integr Circ Sig Process

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“…To further reduce the power consumption of the quantizer, a cyclic ADC, shown in Fig. 10, is used; it combines the loading-free technique and the capacitor reuse technique [18]. In this work, the ratio of the feedback capacitors is 2:1:1 for a 4-bit 1.5bit/stage cyclic ADC.…”

Section: Quantizermentioning

confidence: 99%

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing

Chao

Hsu

Liu

et al. 2012

IEICE Trans. Electron.

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This paper proposes a third-order low-distortion deltasigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a nonoverlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.

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“…Taking into account the requirement of dynamic resolution adaptation, the best way to implement the successive approximation approach is by means of a cyclic A/D converter [13]. In this work, a modified version of the charge sharing approach originally described in [14] has been used.…”

Section: Fractional Part A/d Conversionmentioning

confidence: 99%

Fractional charge packet counting with constant relative resolution

Nascetti

2012

Circuit Theory & Apps

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A charge-to-digital converter concept suitable for pixel-level charge sensitive amplifiers is presented. The circuit implements a technique referred here as fractional charge packet counting, which ensures large dynamic range operation using constant integration time. By means of a particular circuit arrangement a constant number of significant bits is provided as output, thus ensuring a constant relative resolution over the entire dynamic range. A circuit implementing the concepts described above has been designed and simulated. Each block of the circuit is described in details and its characterization is presented. The circuit is capable to convert input currents in the range of 100 fA to 100 nA at 2 ksample/s with a constant resolution of 10 bit without the need of gain switching. Copyright (C) 2010 John Wiley & Sons, Ltd

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Low-Power and Wide-Bandwidth Cyclic ADC With Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application

Cited by 20 publications

References 13 publications

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

A comparator-based cyclic analog-to-digital converter with multi-level input tracking boosted preset voltage

A Third-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing

Fractional charge packet counting with constant relative resolution

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