Low power and write-enhancement RHBD 12T SRAM cell for aerospace applications

Prasad, Govind; Mandi, Bipin Chandra; Ali, Maifuz

doi:10.1007/s10470-020-01786-8

Cited by 16 publications

(8 citation statements)

References 36 publications

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“…As for the influence of process and voltage changes on the performance of SEU and DNU resistance, this subsection sets up 2,000 Monte Carlo model simulations on the SEU and DNU self‐recovery process described in the previous section 24 . In Figure 13, the SEU self‐recovery process for sensitive nodes Q (Figure 13A), QB (Figure 13B), and S0 (Figure 13C) in the memory cell is demonstrated.…”

Section: Simulation Analysis and Comparisonmentioning

confidence: 99%

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Bai,

Chen,

et al. 2023

Circuit Theory & Apps

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SummaryAs the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations.

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Section: Simulation Analysis and Comparisonmentioning

confidence: 99%

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Bai,

Chen,

et al. 2023

Circuit Theory & Apps

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“…The RHBD-12T is fully resistant to single-particle flips. 10 Therefore, the RHBD-12T exhibits a longer read delay and higher power consumption.…”

Section: Multi-redundant Node Reinforcement Technologymentioning

confidence: 99%

A 14T radiation hardened SRAM for space applications with high reliability

Bai,

Qin,

et al. 2023

Circuit Theory & Apps

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SummaryStatic Random Access Memory (SRAM) is vital in aerospace applications, but it may experience soft errors in strong radiation environments. This paper proposes a reconfigurable radiation SRAM with two operating modes catering to different environmental requirements: (1) traditional triple modular redundancy mode used when the radiation environment is strong and (2) SRAM cell expansion mode used when the radiation is not very strong. For example, when the memory capacity of a single module is 8 k, the memory capacity is 8 k in traditional triple modular redundancy mode, but it can be tripled to 24 K in extended mode. As can be obviously seen, this design can adjust the size according to the needs. In SRAM cell expansion mode, the proposed 14T SRAM cell enables the memory to maintain radiation resistance. Compared with DICE, RHBD‐12T, and WHIT, the read speed is improved by 3.8%, 5.7%, and 11.5% respectively, but compared with WE‐QUATRO, the read speed is reduced by 1.9%. The hold static noise margin is 1.378 times than DICE, 1.201 times than WE‐QUATRO, 1.045 times than RHBD‐12T, and 1.14 times than WHIT, respectively. The proposed 14T cell in this paper exhibits the highest critical charge value compared with the other cells. Combined with the expansion mode of the reconfiguration design, it shows great stability.

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“…6, the suggested cell has twelve transistors. Because the write failure rate of the 10T SRAM cell is greater [4,18]. Two more transistors, N3 and N4, have been added to the 10T cell in the proposed cell to prevent write failure.…”

Section: T Rhbd Sram Cellmentioning

confidence: 99%

“…As a result, creating an RHBD cell with a higher frequency combination of all parameters is a challenge. A new radiation-hardened [4] 12T SRAM cell has been proposed to achieve low power dissipation, high write speed, and higher frequency.…”

Section: Introductionmentioning

confidence: 99%

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

Gavaskar¹,

Sivaranjani²,

Elango³

et al. 2022

Wireless Pers Commun

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One of the most critical functions of a computer is memory, as it would be impossible for it to function e ciently without it. The main memory of a computer is known as Random Access Memory (RAM). It stores operating system software, applications, and other data for the central processor unit (CPU) to perform operations swiftly and e ciently. Unfortunately, traditional static RAM (SRAMs) in aerospace applications suffers from high soft error issues such as Single Event Upset (SEU). To overcome the soft error problems, many Radiation-Hardened-Based Designs (RHBD) and Radiation-Hardened-Polar Designs (RHPD) have been developed, such as 12T We-Quatro, twelve-transistor (12T) Dice SRAM cells, and so on. However, they consume more total and static power, as well as have more delay and area. In this article, an RHPD and RHBD 12T SRAM cell is proposed to reduce power dissipation and area overhead. Compared to RHPD, the RHBD 12T SRAM cell devours less total and static power, and RHPD cells have less delay. The proposed SRAM cell is implemented in the 32 x 32 array architecture. The power consumption of a 32 x 32 SRAM array with a 12T RHBD SRAM cell is 1.33mW, which is 10.1% less than a 32 x 32 SRAM array with a 12T RHPD SRAM array is 4.23mW. Cadence virtuoso 6.1.5 at 45 nm Generic Process Design Kit (GPDK) technology le is used to simulate the comparative analysis for the SRAM cell.

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Low power and write-enhancement RHBD 12T SRAM cell for aerospace applications

Cited by 16 publications

References 36 publications

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

Design of SEU and DNU‐resistant SRAM cells based on polarity reinforcement feature

A 14T radiation hardened SRAM for space applications with high reliability

Low-Power SRAM Cell and Array Structure in Aerospace Applications: Single-Event Upset Impact Analysis

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