Low power bulk-driven OTA design optimization using cuckoo search algorithm

Fortes, Anderson; Quirino, Felipe Antunes; Silva, Luiz Augusto da; Girardi, Alessandro

doi:10.1007/s10470-020-01632-x

Cited by 5 publications

(5 citation statements)

References 24 publications

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“…An approach where the OTA behavior is emulated in the digital domain (DIGOTA) was proposed in the literature [27][28][29]. More common and conventional approaches exploit inverter-based stages [30][31][32][33][34][35][36][37], floating-gate devices [38][39][40] or the use of body contacts as input terminals (body driving) [19,[23][24][25][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55] to design OTAs with a rail-to-rail ICMR. Body-biasing techniques [15], where the body terminals are exploited to set the bias point, were proposed in substitution of the tail generator, but in a ULV context, the extremely low voltage swing does not allow to counteract the effect of the PVT variations, due also to the limited body transconductance [50].…”

Section: Introductionmentioning

confidence: 99%

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

et al. 2022

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In this work, an ultra-low-voltage (ULV) technique to improve body-driven current mirrors is proposed. The proposed technique is employed to improve the performance of conventional differential-to-single-ended (D2S) converters which at these low voltages suffer from a low common-mode rejection ratio (CMRR). In addition, the technique aims to improve the performance of the conventional D2S also under a large signal swing and with respect to the process, voltage and temperature (PVT) variations, resulting in a very low distortion, high current mirror accuracy and robust performance. An enhanced body-driven current mirror was designed in a 130nm CMOS technology from STMicroelectronics and an exhaustive campaign of simulations was conducted to confirm the effectiveness of the strategy and the robustness of the results. The enhanced D2S was also employed to design a ULV operational transconductance amplifier (OTA) and a comparison with an OTA based on a conventional D2S was provided. The simulation results have shown that the proposed enhanced D2S allows achieving the ULV OTAs with a CMRR and a PSRR which are 18 and 9 dB higher than the ones obtained with the conventional D2S topology, respectively. Moreover, the linearity performance is also improved as shown by the THD, whose value is decreased of about 5 dB.

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Section: Introductionmentioning

confidence: 99%

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

et al. 2022

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“…The implementation of meta-heuristics depends on the nature of the problem. In general, design methods for analog integrated circuits use heuristics based on natural processes such as Genetic Algorithms [42], Simulated Annealing, Artificial Neural Networks [43,35], Particle Swarm [44,45] and other bio-inspired approaches [29]. These methods have a high probability of finding a solution close to the global optimal after several iterations [1].…”

Section: Optimization Methodsmentioning

confidence: 99%

“…A multi-objective problem can be transformed into a single-objective problem to be solved using only one cost function [29]. In [30], several techniques for constructing a cost function to perform this transformation are presented, with the type of aggregation function being the most used by design methodologies.…”

Section: A Optimization-based Sizingmentioning

confidence: 99%

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

Girardi

De-Oliveira

Ghissoni

et al. 2022

JICS

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Analog integrated circuits are present in most electronic systems. They must be designed carefully in order to achieve the required performance specifications. Although almost half of the design effort in a chip is spent in analog modules, there are not yet a consolidated industry of analog design automation tools capable to fully synthesize analog circuits in a fast and generic way. This is due the fact that automatic or semi-automatic design tools have to deal with high design complexity, which includes several specifications and design variables. A lot of research effort have been done in this field in the past years, proposing methods for automating parts of the design flow, from topology selection to devices sizing and layout generation. This paper presents a review of the state-of-the art in analog design automation methods, focusing on techniques and algorithms used to size robust circuits while efficiently exploring the design space.

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“…The bulk-driven technique [29][30][31] allows rail-to-rail ICMR in ULV amplifiers at the cost of reduced gain and a resistive input impedance component. Bulk-driven amplifiers are surely one of the best alternatives to attain rail-to-rail input-output swing when a well-defined bias or common mode current is required to increase the robustness against process, supply voltage, and temperature (PVT) variations [32][33][34][35][36][37][38][39][40][41][42]. Indeed, the signal-free gate terminals can be used to accurately set the bias current of the different OTA stages.…”

Section: Introductionmentioning

confidence: 99%

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

Centurelli

Sala

Monsurrò

et al. 2022

JLPEA

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In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performance metrics are presented to provide insight into circuit behavior. A 0.3 V supply voltage, subthreshold, ultra-low-power (ULP) OTA, based on the proposed tree-based architecture, was designed in a commercial 130 nm CMOS process. Simulation results show a dc gain higher than 52 dB with a gain-bandwidth product of about 35 kHz and reasonable values of CMRR and PSRR, even at such low supply voltages and considering mismatches. The power consumption is as low as 21.89 nW and state-of-the-art small-signal and large-signal FoMs are achieved. Extensive parametric and Monte Carlo simulations show the robustness of the proposed circuit to PVT variations and mismatch. These results confirm that the proposed OTA is a good candidate to implement ULV, ULP, high performance analog building blocks for directly harvested IoT nodes.

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Low power bulk-driven OTA design optimization using cuckoo search algorithm

Cited by 5 publications

References 24 publications

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

A Differential-to-Single-Ended Converter Based on Enhanced Body-Driven Current Mirrors Targeting Ultra-Low-Voltage OTAs

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

A Tree-Based Architecture for High-Performance Ultra-Low-Voltage Amplifiers

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