Low-power bulk-driven rail-to-rail comparator in 130 nm CMOS technology

Nagy, Lukáš; Arbet, Daniel; Kovac, Martin; Stopjaková, Viera

doi:10.1109/afrcon.2017.8095559

Cited by 4 publications

(4 citation statements)

References 10 publications

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“…A novel low-voltage comparator design that we have proposed in [39] is depicted in Fig.14 (along with the device dimensions). Standard 130 nm CMOS process was selected and the power supply voltage of 400 mV was used.…”

Section: Low-voltage Comparatorsmentioning

confidence: 99%

“…The driving capability was set to f = 500 kHz at capacitive load of 25 pF. The expected performance and other parameters are discussed in more details in [39].…”

Section: Low-voltage Comparatorsmentioning

confidence: 99%

“…Conventional On/Off regulation scheme has been chosen to maximize the charge pump efficiency. This scheme is based on a low-power BD rail-to-rail comparator [39] The charge pump consist of a three-stage dynamic threshold cross-coupled CP structure, where the number of stages was limited by available chip area, which limits the voltage conversion to 2 − 3× [44]. This restriction can be however, avoided by cascading a multiple chip due to identical topology of the individual CP cells.…”

Section: Charge Pump For Self-powered Systemsmentioning

confidence: 99%

“…Comparison of measured and simulated transfer characteristics of the LV comparator proposed in[39]. Comparison of measured and simulated current consumption of the LV comparator proposed in[39].…”

mentioning

confidence: 99%

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Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples

Stopjaková¹,

Rakús²,

Kovac³

et al. 2018

RADIOENGINEERING

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The paper brings an overview of main challenges and design techniques effectively applicable for ultra-low voltage analog integrated circuits in nanoscale technologies. New design challenges linked with a low value of the supply voltage and the process fluctuation in nanotechnologies, such as device models, robustness to process variation, device mismatch and others are discussed firstly. Then, design techniques and approaches to analog integrated circuits towards (ultra) low-voltage systems and applications are described. Finally, examples of basic building blocks of ultra-low voltage analog ICs designed in standard CMOS technology using such design techniques are presented. Finally, the developed circuits are compared to the state-of-the-art solutions in terms of the main parameters and features.

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Section: Low-voltage Comparatorsmentioning

confidence: 99%

“…The driving capability was set to f = 500 kHz at capacitive load of 25 pF. The expected performance and other parameters are discussed in more details in [39].…”

Section: Low-voltage Comparatorsmentioning

confidence: 99%