Low Power, CMOS-MoS2 Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems

Abstract

Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

A Review on MoS2 Properties, Synthesis, Sensing Applications and Challenges

“…The band gap structure of TMDs can be engineered using strain, or dielectric screening [80]. Another low power analogue memory in [81] can be integrated with computing devices to enhance their efficiency. Finding a low contact resistance in TMDs based devices is still a challenge, due to the Fermi level pinning that occurs in metal/2D TMD interface, but in [82] a MoS 2 /MoO3 tunnel field effect (TFET) was introduced, making use of oxygen vacancies in the metal oxide that aligns with the valance band of MoS 2 and assure a good contact with MoS 2 .…”

Emulation of Synaptic Scaling Based on MoS2 Neuristor for Self‐Adaptative Neuromorphic Computing

“…Among these electronic devices, MoS 2 ‐based neuristor is recognized as one of the most promising devices to achieve the Hebbian plasticity and construct the artificial network, due to its extremely low power (≈30 fJ per spike), rich temporal dynamics, high linearity, and comprehensive functions in both chemical synapses and neurons. [ 24–31 ]…”

A Quantum-Well Charge-Trap Synaptic Transistor With Highly Linear Weight Tunability

“…9. Among the devices, although the energy can be increased within an order magnitude if the inference time of 10 ns is increased, it is very probable that the QW CTS device in this work can remain in the group of most energy-efficient synaptic devices, with the merit of full Si processing compatibility [23]- [35].…”