Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate

Efficient systolic multiplications in composite fields for cryptographic systems

“…ASIC, Altera FPGA and Xilinx FPGA Implementations 0 ASIC (TSMC-0.18µm CMOS) implementations: T 0 (ns) is the executing time of non-pipelined designs; T 1 (ns) is the executing time of pipelined designs; A 0 (µm 2 ) is area. 1 Altera FPGA (Stratix II EP2S180F1508C3) implementations: T 2 (ns) is the executing time of non-pipelined designs; T 3 (ns) is the executing time of pipelined designs; A 1 is combinational ALUTs; U 0 is the utilization rate of combinational ALUTs. 2 Xilinx FPGA (Virtex 5 XC5VLX110T) implementations: T 4 (ns) is the executing time of non-pipelined designs; T 5 (ns) is the executing time of pipelined designs; A 2 is slice LUTs; U 1 is the utilization rate of slice LUTs.…”

“…Introduction. Finite field operations have gained increasing importance due to the fact that they are fundamental operations frequently encountered in areas of mathematic [1,5,23,26,27,29,[36][37][38] and engineering [4,7,16,28]. Generally, operations are computed via using a specific basis [2,3,6,9,10,13,[19][20][21][22]25,32,34,35], i.e.…”

Software implementation of AES algorithm on leon3 processor

“…• SubBytes Transformation: It is the only nonlinear substitution in the algorithm which explains the security of the AES [6]. Each entry on the state array is of size 1 byte, each byte is substituted by the corresponding byte from a standard Substitution table, S-box [15].…”

“…Cryptography is important in the security of data transmission. The advanced Encryption standard (AES) algorithm was selected as a data encryption standard by the National Institute of Standards and technology (NIST) in 1997 based on principal criteria of performance, security, flexibility and competence in hardware and software implementation [6]. AES is a famous and strong encryption algorithm which has several advantages in data ciphering, security, simplicity of implementation and low memory requirements [7], but it suffer from some drawbacks like the high computations, pattern in ciphered images, and hardware requirement.Though related work exists for FPGA based AES implementation [8], [9].…”

Fast Hardware Implementations of Inversions in Small Finite Fields for Special Irreducible Polynomials on FPGAs

“…[1] [24][25][26][27][28][29][30]. In particular, inversions in small finite fields are crucial to many cryptographic systems, e.g., AES [39][40][41][42], CLEFIA [43] and Multivariate Public Key Cryptography (MPKC) [44]. AES and CLEFIA use a Substitution-Box (S-Box) [45] in their algorithms, which is generated by determining the multiplicative inverse for a given element; MPKC requires inversions in solving systems of linear equations.…”