Low power design for DSP: methodologies and techniques

Arslan, Tughrul; Erdogan, A.T.; Horrocks, D.H.

doi:10.1016/0026-2692(96)00010-9

Cited by 22 publications

(17 citation statements)

References 65 publications

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“…Based on the FFT algorithm used, radix chosen, size of FFT and the number of channels, a variety of FFT architectures have been proposed in the literature [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. While mapping the FFT algorithm into hardware generally, three [2] or more different architectures are followed [3].…”

Section: General Fft Architecturesmentioning

confidence: 99%

“…The research papers [19][20][21] on methods for motion estimation on a customizable reconfigurable hardware motivate the researchers to search for biologically inspired FFT architectures which might provide the best solution to design a low power FFT. To achieve low power implementation of DSP circuits, pipelining, parallel processing, algebraic transformations, and algorithmic modifications are generally employed [10]. Reducing the physical switching capacitance either by reducing the physical capacitance or by reducing the switching activity is an appropriate solution to achieve low power.…”

Section: Low Power Fft Architectures and Techniquesmentioning

confidence: 99%

“…Reducing the physical switching capacitance either by reducing the physical capacitance or by reducing the switching activity is an appropriate solution to achieve low power. The physical capacitance can be reduced by reducing the complexity of the architecture, while the switching activity can be reduced by an appropriate data encoding method, by proper reordering of the operations, and by using point-to-point data buses [10]. The reduction in complexity and increase in throughput is depicted in [7] for MIMO OFDM system using 4-channel radix-2 3 (R2 3 ) and mixed radix architecture, as R2 3 SDF needs the smallest number of non-trivial multiplications.…”

Section: Low Power Fft Architectures and Techniquesmentioning

confidence: 99%

“…For an edge e from the node U whose l th iteration is scheduled at Fl + u time units to a node V whose l th iteration is scheduled at Fl + v time units in the original DFG with weight w(e), with F as the folding factor, the new weight on the folded edge is calculated using the formula given in Equation 10. [23],…”

Section: Mapping the Dfg On The Array Of Da Butterflies Using Foldingmentioning

confidence: 99%

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Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Paul

Raju²,

Janakiraman³

2014

EURASIP J. Adv. Signal Process.

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A variable length (32~2,048), low power, floating point fast Fourier transform (FP-FFT) processor is designed and implemented using energy-efficient butterfly elements. The butterfly elements are implemented using distributed arithmetic (DA) algorithm that eliminates the power-consuming complex multipliers. The FFT computations are scheduled in a quasi-parallel mode with an array of 16 butterflies. The nodes of the data flow graph (DFG) of the FFT are folded to these 16 butterflies for any value of N by the control unit. Register minimization is also applied after folding to decrease the number of scratch pad registers to (log 2 N − 1) × 16. The real and imaginary parts of the samples are represented by 32-bit single-precision floating point notation to achieve high precision in the results. Thus, each sample is represented using 64 bits. Twiddle factor ROM size is reduced by 25% using the symmetry of the twiddle factors. Reconfigurability based on the sample size is achieved by the control unit. This distributed floating point arithmetic (DFPA)-based design of FFT processor implemented in 45-nm process occupies an area of 0.973 mm 2 and dissipates a power of 68 mW at an operating frequency of 100 MHz. When compared with FFT processor designed in the same technology with multiplier-based butterflies, this design shows 33% less area and 38% less power. The throughput for 2,048-point FFT is 222 KS/s and the energy spent per FFT is 7.4 to 14 nJ for 64 to 2,048 points being one among the most energy-efficient FFT processors.

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Section: General Fft Architecturesmentioning

confidence: 99%

Section: Low Power Fft Architectures and Techniquesmentioning

confidence: 99%

Section: Low Power Fft Architectures and Techniquesmentioning

confidence: 99%

Section: Mapping the Dfg On The Array Of Da Butterflies Using Foldingmentioning

confidence: 99%

See 2 more Smart Citations

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

Paul

Raju²,

Janakiraman³

2014

EURASIP J. Adv. Signal Process.

View full text Add to dashboard Cite

show abstract

“…The reduced switching rate is also beneficial for EMC, with the natural timing variations of asynchronous design giving further benefits. A parallel structure allows algorithmic transformations to be performed, reducing the switching rate at each unit still further [3], [4]. A structure with four independent functional units has been chosen for this DSP architecture, and a block diagram of the overall system architecture is shown in figure 1.…”

Section: A Low-power Dsp Architecturementioning

confidence: 99%