Low-power dividerless frequency synthesis using aperture phase detection

Abstract

A phase-locked-loop (PLL)-based frequency synthesizer incorporating a phase detector that operates on a windowing technique eliminates the need for a frequency divider. This new loop architecture is applied to generate the 1.573-GHz local oscillator (LO) for a Global Positioning System receiver. The LO circuits in the locked mode consume only 36 mW of the total 115-mW receiver power, as a result of the power saved by eliminating the divider. The PLL's loop bandwidth is measured to be 6 MHz, with a reference spurious level of 047 dBc. The front-end receiver, including the synthesizer, is fabricated in a 0.5-m, triple-metal, single-poly CMOS process and operates on a 2.5-V supply.

A 115-mW, 0.5-μm CMOS GPS receiver with wide dynamic-range active filters

“…In addition, an on-chip PLL comprises a VCO, loop filter, charge, pump and phase detectors. The prescaler is eliminated in favor of aperture phase detectors, which only operate at the reference rate, thus reducing power consumption and switching noise [5].…”

A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

“…Consequently, the mean CP output current becomes smaller due to the larger , corresponding to a lower . It is possible to physically eliminate the divider (and its noise contribution) and design a three-state PFD/CP based dividerless PLL as proposed in [17], where the PFD compares the phase of the VCO and Ref at every rising edge of Ref for only a small time window (aperture). However, since the phase detection mechanism remains the same, remains proportional to meaning that it is still reduced by and the CP noise is still multiplied by .…”

“…The noise contribution of the SSPD can be calculated by relating the voltage noise at the SSPD output and the corresponding VCO phase error in steady state: (12) where is the sampling capacitor value. Assuming white noise and using the fact that the SSPD noise is band-limited by due to sampling, the PLL in-band phase noise due to the SSPD can be calculated as 131 Compared with the divider-less PLL in [17], the SSPLL does not only eliminate the physical divider, but also eliminate the divider in the phase domain model. In this sense it is a truly divider-less PLL.…”

A fully-integrated 5 GHz CMOS wireless-LAN receiver

“…The LNA is followed in turn by a double-conversion image-reject architecture known as Weaver architecture [1]. The RF mixers use a passive ring architecture [2], whereas the IF mixers are Gilbert cell multipliers. Thanks to the current-domain outputs of Gilbert cell mixers, addition or subtraction of the downconverted signals requires no additional circuitry.…”

“…Although the blocking performance is slightly worse at this frequency (-22dBm), it is still higher than any possible blocker that might be present at this frequency. The passive ring mixer architecture [2] used for implementing the RF mixers is the reason for this somewhat-reduced blocking performance. When a strong blocker at LO 1 appears at the RF port, it generates a DC voltage at the output of the RF mixer.…”