A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by $N ^{2}$

Abstract

This paper presents a 2.2-GHz low jitter sub-sampling based PLL. It uses a phase-detector/charge-pump (PD/CP) that sub-samples the VCO output with the reference clock. In contrast to what happens in a classical PLL, the PD/CP noise is not multiplied by 2 in this sub-sampling PLL, resulting in a low noise contribution from the PD/CP. Moreover, no frequency divider is needed in the locked state and hence divider noise and power can be eliminated. An added frequency locked loop guarantees correct frequency locking without degenerating jitter performance when in lock. The PLL is implemented in a standard 0.18-m CMOS process. It consumes 4.2 mA from a 1.8 V supply and occupies an active area of 0.4 0.45 mm 2. With a frequency division ratio of 40, the in-band phase noise at 200 kHz offset is measured to be 126 dBc/Hz. The rms PLL output jitter integrated from 10 kHz to 40 MHz is 0.15 ps.

A 8.125–15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop

“…1(b). The divider has been disconnected [1] and there are three different loops which improves the robustness and noise performance of the design across process, voltage and temperature (PVT) variations [2]. The refclk and fbclk are compared using a sample and reset (S/R) which converts the phase difference to voltage.…”

“…The system uses a low-jitter RO PLL, which achieves 160fs RMS jitter at 7.8125 GHz by using a sub-sampling loop [1]. In addition, we present a modified hybrid voltagemode output driver with current-mode equalization and a multi-step duty-cycle corrector used in the transmitter.…”

Jitter-Power minimization of digital frequency synthesis architectures

“…Let's now consider our work on PLL design [9,[12][13]. In contrast to multi-phase clock generators, a PLL usually has only one output.…”

A design methodology to enable sampling PLLs to synthesise fractional-N frequencies

“…Thus the noise, power and hardware consumption of frequency dividers can be ignored in the design process or analysis. Also, the noise from the phase detector and the charge pump will be reduced to 1/N 2 of the original noise density [9], where N is the divisor of a frequency divider in the conventional PLL. However, the conventional SPLL is not able to synthesise fractional-N frequencies and thus cannot achieve the advantages of fractional-N synthesizers just mentioned.…”