To reduce the energy consumption in wireless sensor network transceivers, we propose an approach which combines two tradeoffs. The first tradeoff is between the receiver sensitivity and transmitter output power. The second one is the duty cycle and data rate of the transceiver. The combined approach gives us the optimum choice of noise figure and data rate for a given application and transceiver architecture. Considering a typical transceiver architecture and perfectly synchronized system, we show that the energy consumption can indeed be reduced with this approach compared to choosing either data rate or noise figure arbitrarily. Moreover, in case of a wakeup receiver architecture and slot based MAC protocol, applying this method, we show that there is a different combination of optimum data rate and noise figure value for the wakeup receivers to minimize the wakeup energy.Index terms-Energy, wireless sensor network, noise figure, data rate, duty-cycled radio.I.

To improve interference robustness of wireless communication, spread spectrum techniques are often used. We use the chirp spreading technique along with FSK and PSK binary modulation schemes to obtain interference robust radio communication. The performance of chirped-FSK and chirped-PSK modulation through a white gaussian noise channel is simulated assuming a synchronized clock between transmitter and the receiver. We analyzed and simulated the error probability (BER) of the overall system in the presence of partial band of interference in the channel. The simulated BER is close to the estimated BER and they prove the superior performance of chirp-based modulation in the presence of interference.

An ultra-low-energy Binary Frequency Shift Keying (BFSK) receiver is proposed. It features improved in-band interference tolerance by chirping the transmission frequency. To reduce the receiver power consumption, a novel three-phase passive mixer along with a three stage digitally controlled ring oscillator is proposed, while still allowing quadrature detection. A mixer-first direct conversion receiver architecture moves the required gain to lowest frequency and lowest bandwidth to reduce power consumption. A low power flip-flop based BFSK demodulator is proposed that reduces the baseband power further. The receiver is designed and fabricated in a 65 nm complementary metal-oxide-semiconductor process. It consumes 219 from 1.2 V power supply, while having a sensitivity of for a bit error rate of 0.1% at 2.4 GHz. Except the off-chip 64 MHz clock generation, the total receiver requires 27 pJ/bit. Using a chirped clock spreading of 360 MHz and chirp repetition rate of 1 MHz, it can tolerate up tosignal to interference ratio for all interferer frequencies. This is 13.5 dB better than previously reported in literature and 12 dB better than ideal noncoherent BFSK receiver interference robustness.

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Digital intensive architectures allow for flexibly programmable frequency synthesis. Timing jitter and/or phase noise is an important quality criterion for synthesizers. This paper reviews fundamental limitations for jitter in digital frequency architectures, aiming at finding a basis to compare alternative architectures and optimize jitter performance. It motivates why the product of jitter variance and power consumption is a useful figure of merit (FoM) for optimization, based on fundamental physical limitations. Applying this FoM to multi-phase clock generation leads to the conclusion that circuits with low delay are preferred, favoring a shift register architecture ("ring counter") over a Delay Locked Loop. For a PLL a Jitter-Power FoM is also defined and we show that significant improvements have been made during recent years.