Low power dynamic logic circuit design using a pseudo dynamic buffer

Tang, Fang; Bermak, Amine; Gu, Zhouye

doi:10.1016/j.vlsi.2011.08.003

Cited by 29 publications

(23 citation statements)

References 10 publications

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“…However in footless domino since the domino gates precharge sequentially, the precharge delay becomes critical. Removing redundant switching at the output node was the objective of previously proposed True single phase clock domino logic (TSPC) [9], [10], limited switch dynamic logic (LSDL) [11], [12] and pseudo dynamic buffer (PDB) [13]. Single-phase SP-domino logic [14] and static switching pulse domino logic techniques [15] are proposed to control the redundant switching both at dynamic and output nodes.…”

Section: (4)mentioning

confidence: 99%

“…Short circuit power loss and other power losses are lesser when compared to the dynamic power loss. To reduce the redundant switching only at output node true single phase clock domino logic (TSPC) [9], [10], limited switch dynamic logic (LSDL) [11], [12] and pseudo dynamic buffer (PDB) [13] are given in the literature. To reduce the redundant switching at both dynamic and output nodes Single-phase SP-domino logic [14] and static switching pulse domino logic [15] are given in the literature.…”

Section: Introductionmentioning

confidence: 99%

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Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Mishra¹,

Modanwal²

2017

IJCA

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In wide fan-in domino multiplexors, significant power losses are introduced due to the high switching activity at both dynamic and output nodes. In this paper a multiplexor is proposed with static switching at both dynamic and output nodes. This technique has a control pulse generator circuit which turns on the pull up transistor conditionally for a short duration only. This technique is advanced than previously existing techniques as it has faster response over other existing techniques but lesser power consumption and lesser area required. Simulation is done using 0.18µm CMOS technology. Power consumption of proposed multiplexor is calculated and the results are compared with existing multiplexors for different loading condition, clock frequency and temperature. For capacitance 100 fF, proposed domino multiplexor circuit reduces power consumption by 81.08%, 17.57% and 25.50% as compared to standard footless domino, SP-Domino and SSPD multiplexors.

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Section: (4)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Mishra¹,

Modanwal²

2017

IJCA

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“…1(b).During prechrage phase dynamic node and F_Node is charge to high voltage and output is discharge to low voltage. During evaluation phase dynamic and F_Node is discharge to low voltage and output is charge to high voltage [10]. Here propagation of precharge pulse to the output of the circuit and output logic is unstable.…”

Section: Previous Workmentioning

confidence: 99%

Low Power Dynamic Buffer Circuits

Pandey¹

2012

VLSICS

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In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply. Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.

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“…Static switching mechanisms have also been employed in domino logic circuits to reduce the transitions at the output node. This reduces the dynamic power dissipation and hence the total power consumption [20][21][22][23]. The modification of a domino logic circuit aims at improving the robustness and speed performance of the circuit [24][25][26][27][28][29].…”

Section: Introductionmentioning

confidence: 99%

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

Angeline

Bhaaskaran

2019

ETRI Journal

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Clock Controlled Dual keeper Domino logic structures (CCDD_1 and CCDD_2) for achieving a high‐speed performance with low power consumption and a good noise margin are proposed in this paper. The keeper control circuit comprises an additional PMOS keeper transistor controlled by the clock and foot node voltage. This control mechanism offers abrupt conditional control of the keeper circuit and reduces the contention current, leading to high‐speed performance. The keeper transistor arrangement also reduces the loop gain associated with the feedback circuitry. Hence, the circuits offer less delay variability. The design and simulation of various wide fan‐in designs using 180 nm CMOS technology validates the proposed CCDD_1 and CCDD_2 designs, offering an increased speed performance of 7.2% and 8.5%, respectively, over a conventional domino logic structure. The noise gain margin analysis proves good robustness of the CCDD structures when compared with a conventional domino logic circuit configuration. A Monte Carlo simulation for 2,000 runs under statistical process variations demonstrates that the proposed CCDD circuits offer a significantly reduced delay variability factor.

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Low power dynamic logic circuit design using a pseudo dynamic buffer

Cited by 29 publications

References 10 publications

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Low Power Wide Fan-in Control Pulse Operated Domino Multiplexor with Static Switching

Low Power Dynamic Buffer Circuits

High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

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