Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

Ray, Kanan Bala; Mandal, Sushanta K.; Patro, Shivalal

doi:10.11591/ijeecs.v4.i2.pp333-340

Cited by 5 publications

(1 citation statement)

References 13 publications

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“…Low power VLSI designs [26,27] and low power testing strategies are gaining significant attention of this ubiquitously growing silicon industry. We have analyzed state of the art capture power, shift power and shift and capture power reduction methodologies based on filling of unspecified bits in the test cube.…”

Section: Resultsmentioning

confidence: 99%

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Mitra¹,

Das²

2018

IJEECS

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Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. A significant amount of low-power methodologies are proposed in the relevant literature to address this issue of test mode power consumption and don’t care bit(X) filling approaches are one of them in this fraternity. These don’t care(X) bit filling techniques have drawn the significant attention of industry and academia for its higher compatibility with existing design flow as neither modification of the CUT is required nor they need to rerun the time-consuming ATPG process. This paper presents an empirical survey of those X-bit filling techniques, applied to mitigate prime two types of dynamic power dissipation namely shift power and capture power, occurred during full scan testing.

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Section: Resultsmentioning

confidence: 99%

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Mitra¹,

Das²

2018

IJEECS

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Low Power High Stability SRAM Cell with Combined Effect of Sleep- Stack and Diode Gated Technique

Ray

Patro

2018

2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC)

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Comprehensive Study of Low-Power SRAM Design Topologies

Srivastav,

Tripathi,

Tiwari

et al. 2024

EEENG

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The need for low power in portable and smart devices is the demand to be fulfilled for sustaining the semiconductor industry. Static Random Access Memory (SRAM) is the main part of the core design in chips. It is important to reduce the leakage power consumption during the steady mode of the device for the long run of the battery. This article is about the study of different modules using pre-existing low power. Application of different methods other than lowering the supply voltage leads to an increment in the number of transistors in conventional 6T (six transistor) SRAM cells like 7T to 14T. Power gating and the Multi-threshold complementary metal oxide semiconductor (MTCMOS) technique is the most relevant method. Hybrid low power techniques are in high demand because it shows better results than using individual techniques. However, the biggest challenge is to maintain the area and delay as well. FinFET came into the scenario to overcome the leakage power and short channel effect due to scaling in CMOS. Comparative study analysis shows that FinFET decreases the overall power and delay even when the number of transistors increases. A comparison was done between 6T, 8T, and 10T using FinFET and CMOS in a paper, and concluded that FinFET shows 77.792% improved write power.

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Low Power FGSRAM Cell Using Sleepy and LECTOR Technique

Cited by 5 publications

References 13 publications

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

A Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems

Low Power High Stability SRAM Cell with Combined Effect of Sleep- Stack and Diode Gated Technique

Comprehensive Study of Low-Power SRAM Design Topologies

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