Low power HEVC software decoder for mobile devices

Raffin, Erwan; Nogues, Erwan; Hamidouche, Wassim; Tomperi, Seppo; Pelcat, Maxime; Ménard, Daniel

doi:10.1007/s11554-015-0512-8

Cited by 20 publications

(13 citation statements)

References 19 publications

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“…In this context, the dynamic frequency selection algorithm proposed by Raffin et al [11] has been integrated in the openHEVC decoder. Here, the operating frequency of the processor is controlled based on the estimated complexity of the subsequent frame (assessed using the moving weighted average of the complexities of previously decoded frames).…”

Section: ) Energy Consumption Behavior-offline Video Playbackmentioning

confidence: 99%

“…More state-of-the-art solutions manipulate the motion compensation and in-loop filtering operations in HEVC [6] [7] or adopt Dynamic Voltage and Frequency Scaling (DVFS) [8] - [11] techniques to reduce the decoder's power consumption. However, the state-of-the-art methods in the literature do not exploit the variations of the computational complexity that exist between different decoding operations to determine the optimum coding parameters at the encoder itself.…”

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confidence: 99%

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Decoding-Complexity-Aware HEVC Encoding Using a Complexity–Rate–Distortion Model

Mallikarachchi

Talagala

Arachchi

et al. 2018

IEEE Trans. Consumer Electron.

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Abstract-The energy consumption of Consumer Electronic (CE) devices during media playback is inexorably linked to the computational complexity of decoding compressed video. Reducing a CE device's the energy consumption is therefore becoming ever more challenging with the increasing video resolutions and the complexity of the video coding algorithms. To this end, this paper proposes a framework that alters the video bit stream to reduce the decoding complexity and simultaneously limits the impact on the coding efficiency. In this context, this paper (i) first performs an analysis to determine the trade-off between the decoding complexity, video quality and bit rate with respect to a reference decoder implementation on a General Purpose Processor (GPP) architecture. Thereafter, (ii) a novel generic decoding complexity-aware video coding algorithm is proposed to generate decoding complexity-rate-distortion optimized High Efficiency Video Coding (HEVC) bit streams. The experimental results reveal that the bit streams generated by the proposed algorithm achieve 29.43% and 13.22% decoding complexity reductions for a similar video quality with minimal coding efficiency impact compared to the state-of-the-art approaches when applied to the HM16.0 and openHEVC decoder implementations, respectively. In addition, analysis of the energy consumption behavior for the same scenarios reveal up to 20% energy consumption reductions while achieving a similar video quality to that of HM 16.0 encoded HEVC bit streams.

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Section: ) Energy Consumption Behavior-offline Video Playbackmentioning

confidence: 99%

mentioning

confidence: 99%

Decoding-Complexity-Aware HEVC Encoding Using a Complexity–Rate–Distortion Model

Mallikarachchi

Talagala

Arachchi

et al. 2018

IEEE Trans. Consumer Electron.

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“…On the HEVC side, although a few works tackle the decoder design and optimization (e.g., [15]), latest research has focused more on the encoder as it is approximately 100 times more complex [4]. In this context, the majority of the work includes algorithmic optimization with various objectives such as power and complexity reduction, encoding time enhancement, etc.…”

Section: Related Workmentioning

confidence: 99%

Machine Learning-Based Quality-Aware Power and Thermal Management of Multistream HEVC Encoding on Multicore Servers

Iranfar

Zapater

Atienza

2018

IEEE Trans. Parallel Distrib. Syst.

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The emergence of video streaming applications, together with the users' demand for high-resolution contents, has led to the development of new video coding standards, such as High Efficiency Video Coding (HEVC). HEVC provides high efficiency at the cost of increased complexity. This higher computational burden results in increased power consumption in current multicore servers. To tackle this challenge, algorithmic optimizations need to be accompanied by content-aware application-level strategies, able to reduce power while meeting compression and quality requirements. In this paper, we propose a machine learning-based power and thermal management approach that dynamically learns and selects the best encoding configuration and operating frequency for each of the videos running on multicore servers, by using information from frame compression, quality, encoding time, power, and temperature. In addition, we present a resolution-aware video assignment and migration strategy that reduces the peak and average temperature of the chip while maintaining the desirable encoding time. We implemented our approach in an enterprise multicore server and evaluated it under several common scenarios for video providers. On average, compared to a state-of-the-art technique, for the most realistic scenario, our approach improves BD-PSNR and BD-rate by 0.54 dB, and 8%, respectively, and reduces the encoding time, power consumption, and average temperature by 15.3%, 13%, and 10%, respectively. Moreover, our proposed approach increases BD-PSNR and BD-rate compared to the HEVC Test Model (HM), by 1.19 dB and 24%, respectively, without any encoding time degradation, when power and temperature constraints are relaxed.

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“…In the context of mobile and hand-held devices, the authors of [24,23] describe several strategies for power optimization of a real-time software HEVC decoder on a NEON architecture. These strategies exploit dataparallelism, task-parallelism, and dynamic voltage-frequency scaling (DVFS); however, only one type of core in an ARM big.LITTLE AMP is used at a time.…”

Section: Related Workmentioning

confidence: 99%

Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors

Rodríguez‐Sánchez

Quintana–Ort́ı

2016

J Real-Time Image Proc

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Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload.The recent HEVC standard, which offers several high-level parallelization strategies, is an important application that can benefit from an implementation tailored for the low-power AMPs present in many current mobile or hand-held devices. In this scenario, we present an architecture-aware implementation of an HEVC decoder that embeds a criticality-aware scheduling strategy tuned for a Samsung Exynos 5422 system-on-chip furnished with an ARM R big.LITTLE TM AMP. The performance and energy efficiency of our solution is further enhanced by exploiting the NEON TM vector engine available in the ARM big.LITTLE architecture. Experimental results expose a 1080p real-time HEVC decoding at 24 frames/sec, and a reduction of energy consumption over 20%.

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Low power HEVC software decoder for mobile devices

Cited by 20 publications

References 19 publications

Decoding-Complexity-Aware HEVC Encoding Using a Complexity–Rate–Distortion Model

Decoding-Complexity-Aware HEVC Encoding Using a Complexity–Rate–Distortion Model

Machine Learning-Based Quality-Aware Power and Thermal Management of Multistream HEVC Encoding on Multicore Servers

Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors

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