Low-Power Highly Selective Channel Filtering Using a Transconductor–Capacitor Analog FIR

Abstract

Analog Finite-Impulse-Response (AFIR) filtering is proposed to realize low power channel selection filters for Internet-of-Things receivers. High selectivity is achieved using an architecture based on only a single -time-varyingtransconductance and integration capacitor. The transconductance is implemented as a Digital-to-Analog Converter and is programmable by an on-chip memory. The AFIR operating principle is shown step-by-step, including its complete transfer function with aliasing. The filter bandwidth and transfer function are highly programmable through the transconductance coefficients and clock frequency. Moreover, the transconductance programmability allows an almost ideal filter response to be realized by careful analysis and compensation of the parasitic circuit impairments. The filter, manufactured in 22nm FDSOI, has an active area of 0.09mm 2 . Its bandwidth can be accurately tuned from 0.06 to 3.4MHz. The filter consumes 92µW from a 700mV supply. This low power consumption is combined with a high selectivity: f -60dB /f -3dB =3.8. The filter has 31.5dB gain and 12nV/ √ Hz input-referred noise for a 0.43MHz bandwidth. The OIP3 is 28dBm, independent of the frequency offset. The outputreferred 1dB-compression point is 3.7dBm, and the in-band gain compresses by 1dB for an -3.7dBm out-of-band input signal, while still providing >60dB of filtering.

A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection

“…Besides featuring the best stopband rejection, the proposed filter maintains better in-/out-of-band linearity, power consumption, and noise performance than [20] and [16]. Although [19] achieves higher gain and lower power consumption using an AFIR filtering technique, its linearity, and noise performances are significantly worse.…”

“…Recently, various new techniques have been introduced for high-performance LPFs targeting scaled CMOS. This includes charge-sharing (CS) infinite-impulse response (IIR) [15]- [18], analog finite-impulse response (AFIR) [19], filtering by aliasing [20], and flipped/coupled source followers (FSFs/CSFs) [21], [22]. Tohidian et al [15] introduced a high-order (i.e., 7th) IIR LPF by means of adding more clock phases and history capacitors to the conventional first-order IIR filter.…”

“…Lulec et al [17] introduced an idea to create two complex conjugate-pole pairs in a conventional IIR filter by means of a feedback path through a sampling capacitor (C S ). In [19], a low-power AFIR was introduced that contains a single inverter-based g m -C integrator implemented as a digitalto-analog converter (DAC). A filtering-by-aliasing approach introduced in [20] is based on two integrate-and-dump circuits, each taking a benefit of a time-varying resistor [i.e., R(t) = R(t + T s )] to make an equivalent FIR filter with the desired impulse response.…”

A 0.015mW quasi-passive reconfigurable complex band-pass filter for analog baseband

“…Literature [10] proposed a low power and high linearity bandpass filter (BPF), which achieves approximately 6 dBm in-band IIP 3 with the power consumption of 7.6 mW. The low-power highly selective channel filtering using a G m -C analog FIR [11] was proposed for the Internet-of-Thing receivers. The filter achieved a 31.5 dB gain for a 0.43 MHz bandwidth, and it consumed a dc power of 92 µW.…”

Interference-robust CMOS receivers for IoT : Highly linear RF frontends at low power

“…An example of analog DT-FIR low-pass filter implemented using a g m − C integrator [70] is shown in Fig. 2.17.…”