Low power methodology and design techniques for processor design

Brennan, J.P.; Dean, A.; Kenyon, Susan M.; Ventrone, Sebastian

doi:10.1145/280756.280931

Cited by 10 publications

(4 citation statements)

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“…Low-power products have traditionally been custom designed, with the help of accurate power estimators and power reporting tools, in order to deliver first-pass silicon that meets the target power specification. Typically, a semicustom, cell-based, design methodology was considered less attractive for low power products because FIGURE The power wheel represents the components of a low power design methodology (from [1]).…”

Section: Low Power Design Methodologymentioning

confidence: 99%

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Low Power Design for ASIC Cores

Dean¹,

Garrett

Stan

et al. 2000

VLSI Design

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Section: Low Power Design Methodologymentioning

confidence: 99%

“…In this paper, we present the process and techniques by which we achieved the low power design of a DSP core for mobile (battery powered) applications using a semicustom methodology. These techniques can be used for other semicustom designed cores and have been incorporated into the low power design methodology shown in Figure 2 [1].…”

Section: Low Power Designmentioning

confidence: 99%

Low Power Design for ASIC Cores

Dean¹,

Garrett

Stan

et al. 2000

VLSI Design

Self Cite

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“…ith the emerging technologies in internet-of-things (IOT) and artificial intelligence, there is a growing demand for the high-performance microcontroller unit (MCU), which integrates central processing unit (CPU), memory, digital, analog, input/output and other components for signal and data processing. However, the development of MCU technology has been largely bottlenecked by the power consumption which can be hardly further reduced in advanced fabrication technology nodes [1][2][3] . In general, the power consumption in MCU is minimized through distributing different status like active, sleep and deep sleep modes in analog, digital, memory and input/output (I/O) components according to different circuit functions [4] .…”

Section: Introductionmentioning

confidence: 99%

Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

Zhao

Zhou

Zhu³

et al. 2021

IEEE J. Electron Devices Soc.

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The fast development in microcontroller unit (MCU) technology has urged continuous decreasing in power consumption by different assignment of operating status among devices. In this work, we focused on the ultrahigh Vth (UHVT) transistor and used gate oxide thickness and Vth implantation co-optimization to minimize the gate leakage current towards low-power MCU applications. Based on the 55 nm node, it has been found both theoretically and experimentally that the leakage level has been significantly reduced at different temperature in n-FET, p-FET, data flip-flop (DFF) and inverter (INV). Upon MCU testing under active, sleep and deep sleep modes, obvious decrease in the power consumption is also achieved, providing a promising optimization approach towards a better balance between the speed and power in modern MCU technology.

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“…In this work, modern digital low power methodologies, mostly meant to achieve the optimal trade-off between performance and energy consumption (e.g. [7,8]), are adopted and innovatively targeted to the specific needs of serial powering for pixel detector modules. In this context, digital optimization is not only focused on the average power budget, but strongly involves minimization of peak power taking into account the impact of local decoupling on power variations.…”

Section: Introductionmentioning

confidence: 99%

Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

et al. 2017

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A: A dedicated power analysis methodology, based on modern digital design tools and integrated with the VEPIX53 simulation framework developed within RD53 collaboration, is being used to guide vital choices for the design and optimization of the next generation ATLAS and CMS pixel chips and their critical serial powering circuit (shunt-LDO). Power consumption is studied at different stages of the design flow under different operating conditions. Significant effort is put into extensive investigations of dynamic power variations in relation with the decoupling seen by the powering network. Shunt-LDO simulations are also reported to prove the reliability at the system level. K: Digital electronic circuits; Front-end electronics for detector readout; Simulation methods and programs; VLSI circuits 1Corresponding author.

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Low power methodology and design techniques for processor design

Cited by 10 publications

References 0 publications

Low Power Design for ASIC Cores

Low Power Design for ASIC Cores

Gate Oxide and Implantation Process Co-Optimization for Low-Power MCU Applications

Advanced power analysis methodology targeted to the optimization of a digital pixel readout chip design and its critical serial powering system

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