Low Power Design for ASIC Cores

Dean, A.; Garrett, David; Stan, Mircea R.; Ventrone, Sebastian

doi:10.1155/2001/90464

Cited by 2 publications

(2 citation statements)

References 2 publications

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“…Logic design techniques for reducing active power include drive strength reduction for non-timing-critical logic paths, glitch-free combinational logic, disabling unobserved combinational blocks [22], gating the clock locally for registers that retain logic state across several cycles, allowing clock skew to reduce simultaneous switching, and double-edged clocking [23]. Managing power at the architectural level can provide significant leverage in reducing chip power, and will be discussed in more depth later in this paper.…”

Section: Power Managementmentioning

confidence: 99%

Designing mega-ASICs in nanogate technologies

Lackey

Zuchowski

Koehl

2003

Proceedings of the 40th Annual Design Automation Conference

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This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities possible in the latest silicon technologies. Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas are presented. Lastly, this paper discusses the integration of multiple functional components (previously organized as systems of multiple chips from multiple design sources and technologies) into a single chip product.

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Section: Power Managementmentioning

confidence: 99%

Designing mega-ASICs in nanogate technologies

Lackey

Zuchowski

Koehl

2003

Proceedings of the 40th Annual Design Automation Conference

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“…Trading off power for performance must be accomplished differently for each design because of the different market requirements [30]. Trading off power for performance must be accomplished differently for each design because of the different market requirements [30].…”

Section: Low-power Design and Voltage Islandsmentioning

confidence: 99%

The IBM ASIC/SoC methodology—A recipe for first-time success

Doerre

Lackey

2002

IBM J. Res. & Dev.

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This methodology is used by both IBM ASIC and SoC designers, as well as OEM customers.A key focus of the IBM ASIC/SoC methodology, outlined in the first section of this paper, is the first-time-right methods of design and verification that maximize correct operation of the chip upon product integration. The second section of this paper describes advances in methodology that deal with the physical effects of shrinking device geometries and enable design using the performance and density capabilities available in the new technologies, and methodology advances that have improved design turnaround time (TAT) for large, complex designs. Upcoming nanometerlevel technologies present new opportunities to integrate systems on a single chip, including functional components of mixed libraries and mixed analog and digital design. The final section of this paper outlines strategies that are enabling SoC design at these levels.

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Low Power Design for ASIC Cores

Cited by 2 publications

References 2 publications

Designing mega-ASICs in nanogate technologies

Designing mega-ASICs in nanogate technologies

The IBM ASIC/SoC methodology—A recipe for first-time success

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