The IBM ASIC/SoC methodology—A recipe for first-time success

Doerre, George; Lackey, David E.

doi:10.1147/rd.466.0649

Cited by 7 publications

(8 citation statements)

References 14 publications

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“…Advanced semiconductor circuit designs can contain more than 100 million circuits with interconnection densities in the range of 10 6 to 10 8 cm À2 . Consequently, products with the lowest cost, smallest size, and best performance have often utilized system-on-chip (SOC) product solutions in which the system functions can be manufactured on a single wafer using compatible semiconductor processes [10]. For many product applications, system complexity and manufacturing process integration needs do not permit a solution on one chip; instead, heterogeneous semiconductor technologies are required.…”

Section: Introductionmentioning

confidence: 99%

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

et al. 2005

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System-on-Package (SOP) technology based on silicon carriers has the potential to provide modular design flexibility and highperformance integration of heterogeneous chip technologies and to support robust chip manufacturing with high-yield/low-cost chips for a wide range of two-and three-dimensional product applications. Key technology enablers include silicon through-vias, high-density wiring, high-I/O chip interconnection, and supporting test and assembly technologies. The silicon through-vias are a key feature permitting efficient area array signal, power, and ground interconnection through these thinned silicon packages. Highdensity wiring and high-density chip I/O interconnection can enable tight integration of heterogeneous chip technologies which approximate the performance of an integrated system-on-chip with a ''virtual chip'' using the silicon package for integration. Silicon carrier fabrication leverages existing manufacturing capability and mid-UV lithography to provide very dense package wiring following CMOS back-end-of-line design rules. Further, the thermal expansion of the silicon carrier package matches the chip, which helps maintain reliability even as the high-density chip microbump interconnections scale to smaller size. In addition to heterogeneous chip integration, SOP products may leverage the integration of passive components, active devices, and electrooptic structures to enhance system-level performance while also maintaining functional test capability and known good chips when needed. This paper describes the technical challenges and recent progress made in the development of silicon carrier technology for potential new applications.

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Section: Introductionmentioning

confidence: 99%

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

et al. 2005

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“…IBM's ASIC Design Methodology [9] has deployed numerous and sweeping examples of successful integrations within the tool flow, including:…”

Section: Tool Integration Focusmentioning

confidence: 99%

“…• Extended Design-For-Test techniques able to provide the increased test data volume of huge gate counts, and able to identify delay-based defects, the need for which increases with decreasing circuit and process geometries [9].…”

Section: Design Qualitymentioning

confidence: 99%

“…Hierarchical physical design approaches become necessary for integrating a design of functional/technology "islands" [9]. Uniquely by island, a physical architecture can be defined including circuit row topology, power distribution structure, Vdd supply, transistor threshold and/or transistor voltage bias supply, and island-specific circuitry for voltage level shifting, voltage regulation and switching [26], capacitive decoupling, and electrostatic discharge.…”

Section: Technology "Islands"mentioning

confidence: 99%

“…IBM's eDesign ™ and TheGuide™ are used and will further evolve to support increasingly collaborative and distributed design [9], and multi-threaded hierarchical design flows whose required design steps vary by functional block.…”

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confidence: 99%

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Designing mega-ASICs in nanogate technologies

Lackey

Zuchowski

Koehl

2003

Proceedings of the 40th Annual Design Automation Conference

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This paper discusses challenges the designer faces in integrating entire system product designs, containing tens or even hundreds of millions of logic gates, into single chip solutions now within reach using circuit densities possible in the latest silicon technologies. Managing designs of this size presents a new dimension of issues, and managing the physical and electrical effects of these high density device geometries presents another; solutions in both these areas are presented. Lastly, this paper discusses the integration of multiple functional components (previously organized as systems of multiple chips from multiple design sources and technologies) into a single chip product.

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Designing mega-ASICs in nanogate technologies

Lackey¹,

Zuchowski²,

Koehl³

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

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The IBM ASIC/SoC methodology—A recipe for first-time success

Cited by 7 publications

References 14 publications

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection

Designing mega-ASICs in nanogate technologies

Designing mega-ASICs in nanogate technologies

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