Low-power MPEG-4 video encoder design

Denolf, Kristof; Chirila-Rus, A.; Verkest, D.

doi:10.1109/sips.2005.1579880

Cited by 6 publications

(10 citation statements)

References 7 publications

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“…VIDEO ENCODER Our energy consumption model is based on IMEC's MPEG-4 Simple Profile video encoder with an ASIC implementation [4]. The encoder energy consumption consists of two parts: memory access and functional processing (e.g., motion estimation, texture coding, etc.).…”

Section: Energy Consumption Model Of a Mpeg-4mentioning

confidence: 99%

“…To reduce energy cost, both memory hierarchy optimization and algorithmic tuning are carried out in this encoder design. Interested readers are referred to [4] for more details. The resulting IMEC MPEG-4 encoder is able to process (up to) 4CIF video at 30 frames per second (fps) with a low power consumption of 70mW in a 180nm, 1.62V UMC technology.…”

Section: Energy Consumption Model Of a Mpeg-4mentioning

confidence: 99%

“…In particular, the energy numbers for each memory and functional blocks are calculated using the Synopsys power compiler (see [4] for more detailed). By examining the simulation results, a set of memories that make significant contributions in energy consumption can be identified, which include both big memories that store the original frame and the search area (for motion estimation purpose), and those smaller ones (but accessed more frequently) which store MBs or 8 × 8 blocks.…”

Section: Computation Of Encoder Energy Consumptionmentioning

confidence: 99%

“…Generally, the energy cost decreases with larger QP . There are several reasons behind this behavior: 1) in our motion estimation algorithm [4], larger QP would relax the block matching criteria and reduces the number of SAD computations; 2) with our intelligent DCT processing [4], larger QP would allow more MBs to be coded in SKIP mode (i.e., no DCT) or directional DCT mode (i.e., one dimension DCT) instead of the most complex 8 × 8 full DCT mode.…”

Section: Empirical Encoder Energy Modelmentioning

confidence: 99%

“…As a result, when compared to the INTRA mode, the extra energy cost for INTER mode in motion estimation is offset by the energy savings in DCT processing. In summary, with the IMEC encoder design [4], for certain sequences, increasing the INTRA refresh rate β may not reduce encoder energy consumption. …”

Section: Empirical Encoder Energy Modelmentioning

confidence: 99%

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Modelling Energy Consumption of an ASIC MPEG-4 Simple Profile Encoder

Gan

Denolf

Lafruit

et al. 2007

Multimedia and Expo, 2007 IEEE International Conference On

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In wireless video streaming, it is desirable to minimize the energy consumption of mobile devices while achieving target video quality. For this purpose, it is essential to model (i.e., estimate) the energy cost of the streaming system, including both video encoder and wireless transmission energy, under different system settings. In this paper, an energy consumption model is proposed for a MPEG-4 simple profile encoder implemented in ASIC. Our proposed model consists of three major steps: 1) compute the encoder energy consumption through power simulations; 2) empirically model the impact of configuration parameters through curve fitting; and 3) online updating of model coefficients. Experimental results show that our proposed model works well for different types of video, and the average estimation error is below 6%.1. INTRODUCTION With the fast development of video coding, hardware, and wireless communication technologies, wireless video streaming is expected to be one of the killer applications in the coming era. Due to the increased energy requirements of signal processing and wireless transmission, the limited battery capacity of mobile devices has become a major bottleneck.When streaming live video across wireless links, two main sources of energy consumption are video coding and wireless transmission. In most of the state-of-the-art video encoders and wireless transmitters, it is possible to adjust the configuration parameters (i.e., "knobs") based on varying channel conditions and/or video content to improve system performance. For instance, in a bad channel state, to reduce the effect of bit errors on the received video quality, many options are available, including (but not limited to): 1) increasing the INTRA refresh rate, 2) using specific error resilience tools such as resynchronization markers and data partitioning, 3) increasing channel coding rate, and 4) increasing the transmission power of the antenna, etc. This enables system performance optimization, such as minimizing the energy consumption of the entire system (including both video coding and wireless transmission), while satisfying end-users' requirement on the perceived video quality.To this end, it is essential to model (i.e., make an estimation of) the energy consumption under different system settings, so that the optimal operation point can be chosen given the system state. Although the modelling of wireless transmission energy has been extensively studied in the literature, the work on video encoder is rather limited.In [1], a H.263 encoder with eight encoding modes is used. It is assumed that the encoder is running on a TI DSP, and the power consumption of each mode is estimated using the "iprof" software [1]. Since only one test sequence is used in the experiment, it is not clear whether the video content has an impact on the encoder's energy consumption.In [2], two "knobs" are considered for a H.263 encoder: bitrate and the INTRA refresh rate. The power consumption is measured on a laptop computer running the software H.263 encoder...

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Section: Energy Consumption Model Of a Mpeg-4mentioning

confidence: 99%

Section: Energy Consumption Model Of a Mpeg-4mentioning

confidence: 99%

Section: Computation Of Encoder Energy Consumptionmentioning

confidence: 99%

Section: Empirical Encoder Energy Modelmentioning

confidence: 99%

Section: Empirical Encoder Energy Modelmentioning

confidence: 99%

See 3 more Smart Citations

Modelling Energy Consumption of an ASIC MPEG-4 Simple Profile Encoder

Gan

Denolf

Lafruit

et al. 2007

Multimedia and Expo, 2007 IEEE International Conference On

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A reconfigurable computing platform for real time embedded applications

Say

Bazlamaçcı

2012

Microprocessors and Microsystems

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, 136 pages Today's reconfigurable devices successfully combine 'reconfigurable computing machine' paradigm and 'high degree of parallelism' and hence reconfigurable computing emerged as a promising alternative for computing-intensive applications. Despite its superior performance and lower power consumption compared to general purpose computing using microprocessors, reconfigurable computing comes with a cost of design complexity. This thesis aims to reduce this complexity by providing a flexible and user friendly development environment to application programmers in the form of a complete reconfigurable computing platform. ACKNOWLEDGMENTS First, I must thank my advisor, Assoc. Prof. Dr. Cüneyt Fehmi Bazlamaçcı for his support during both my MSc and PhD studies. This work would not have been possible without his guidance, advice, criticism and encouragements. I would also like to express my gratitude to my dissertation committee members; Prof. Dr. Hasan Cengiz Güran and Prof. Dr. Volkan Atalay. They have provided many useful insights and helpful feedback during this process. I would like to acknowledge my company ASELSAN Inc. for the encouragement and support during my MSc and PhD studies. Last but not the least, I must thank my wife,Şifa Say, whose love and support are crucial for anything I have ever accomplished. I also thank our kids, Eren and Berra for bringing me sunshine and happiness.

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