Low-power pipeline ADC for wireless LANs

Arias, J.; Boccuzzi, V.; Quintanilla, L.; Enríquez, Lourdes; Bisbal, D.; Banu, M.; Barbolla, J.

doi:10.1109/jssc.2004.831477

Cited by 61 publications

(17 citation statements)

References 12 publications

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“…20). Among many ADC architectures, pipeline converters have proven to be a very efficient architecture for meeting the low power consumption and high input bandwidth requirements of DVB-H standard [17,18]. Moreover, the evolution of CMOS technology has made the choice of a continuous-time Sigma-Delta (RD) architecture very attractive because its power efficiency.…”

Section: Adcmentioning

confidence: 99%

RF and mixed signal circuits for a DVB-H receiver

Khemchandani

Pino

López-Morillo

et al. 2010

Analog Integr Circ Sig Process

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This paper presents a tutorial on RF and mixed signal circuits design for a digital video broadcastinghandheld tuner. A detailed description of the wideband low noise amplifier, the mixer, the synthesizer and the ADC, which are the most challenging components of a receiver, are carried out. Requirements relative to frequency range, sensitivity, noise figure, linearity, phase noise gain and dynamic range are discussed. The LNA uses a cascode configuration, combining a resistive loaded LNA with a conventional resistive shunt-feedback, in order to achieve a low power, low noise and wide bandwidth. The mixer uses a classical Gilbert cell configuration. The VCO employs techniques like emitter degeneration, capacitor divider, and optimum bias for minimum noise to improve phase noise requirements and oscillation amplitude. There are two ADC structures, one of which is a delta sigma ADC. The blocks are implemented in a AMS 0.35 lm BiCMOS process.

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Section: Adcmentioning

confidence: 99%

RF and mixed signal circuits for a DVB-H receiver

Khemchandani

Pino

López-Morillo

et al. 2010

Analog Integr Circ Sig Process

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“…However, the pseudo differential architecture [6] could not provide a good dynamic performance for the relatively high frequency inputs due to its non-differential nature and hence the higher evenorder harmonics compared with that of the fully differential one. Also, the time-interleaving architecture [7,8] could not show a good dynamic performance due to the mismatches between the time-interleaving channels and usually needs complex calibration scheme to correct the mismatches [9]. The opamp sharing architecture only needs half the number of opamps thereby could reduce significant power consumption [10][11][12][13].…”

Section: Adc Architecturementioning

confidence: 99%

Design of an ADC for subsampling video applications

Zeng

Zhang

et al. 2006

Analog Integr Circ Sig Process

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This paper describes a 10 bit 30 Msample/s (MSPS) CMOS analog-to-digital converter (ADC) for highspeed signal processing, especially for subsampling applications, for example digital video broadcasting over cable (DVB-C), terrestrial (DVB-T) and handheld (DVB-H) systems. The proposed pipelined ADC shows a good figure-ofmerit (FoM). It adopts a power efficient amplifier sharing technique, a symmetrical gate-bootstrapping technique with modified timing for the bottom-sampling switch of a wideband sample-and-hold (S/H) circuit, a proposed stable highswing bias circuit for a wide-swing gain-boosting telescopic amplifier. The measured differential and integral nonlinearities of the prototype in a 0.25-µm CMOS technology show less than 0.4 least significant bit (LSB) and 0.85 LSB respectively at full sampling rate. The ADC exhibits higher than 9 effective number of bits (ENOB) for input frequencies up to about 60 MHz, which is the fourfold Nyquist rate (fs/2), at 30 MSPS. The ADC consumes 60 mW from a 3-V supply and occupies about 1.36 mm 2 .

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“…CMOS ADCs with sampling rate more than 100Msps and resolution more than 10bit are widely used in optical communication system, wireless and wired broadband communication systems [1]. Pipeline is the appropriate architecture widely used in this class of ADCs for its reasonable trade-offs among sampling rate, resolution and power.…”

Section: Introductionmentioning

confidence: 99%

“…This value can be used to calibrate the channel mismatch such as capacitance mismatch and OTA gain mismatch between ADC (A) and ADC (B). Several digital calibration algorithms for split ADC are proposed [1]- [6]. But for high speed pipeline ADC design, the digital calibration for split ADC has three difficulties: 1) In Fig.…”

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confidence: 99%

A 12Bit 200Msps Spilt-Based Pipeline ADC Design

Lin¹,

San²,

Tian³

2016

IJIEE

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Abstract-This paper presents a 12bit 200Msps pipeline ADC fabricated in TSMC 0.18um CMOS technology. For high resolution pipeline ADC design, the operation speed is limited by sampling capacitance load of OTA inside the ADC. The proposed ADC is realized in split-based pipeline architecture, sampling capacitance of ADC is separated into two channels. Each channel only has half capacitance, which reduce capacitive loading of OTAs in each channel and realize high speed operation of the ADC. The ADC achieves an SNDR of 64.7dB, SFDR of 86.3dB with analog input frequency of 10MHz, sampling frequency of 100MHz and differential amplitude of 1.25Vpp without digital calibration. The power dissipation of ADC is 356mW at 1.8V supply.Index Terms-OTA, pipeline ADC, split-based. I. INTRODUCTIONCMOS ADCs with sampling rate more than 100Msps and resolution more than 10bit are widely used in optical communication system, wireless and wired broadband communication systems [1]. Pipeline is the appropriate architecture widely used in this class of ADCs for its reasonable trade-offs among sampling rate, resolution and power. To realize the high sampling rate and high resolution pipeline ADC, the OTA to drive large sampling capacitance inside MDAC becomes the bottleneck which limits the sampling rate of ADC. Split ADC architecture is the useful method to reduce the capacitance need to be driven by OTA in pipeline ADC [2]. Split-based pipeline ADC consists of 2 independent ADCs with the same circuit structure which shares a same SHA [3]. The block diagram of traditional split ADC is shown in Fig. 1, The output code of ADC (A) and ADC(B) are X A and X B respectively. By average calculation, the final output code of the ADC can be written as Eq. 1, and difference between outputs of 2 ADCs can be written as Eq. 2.

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Low-power pipeline ADC for wireless LANs

Cited by 61 publications

References 12 publications

RF and mixed signal circuits for a DVB-H receiver

RF and mixed signal circuits for a DVB-H receiver

Design of an ADC for subsampling video applications

A 12Bit 200Msps Spilt-Based Pipeline ADC Design

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