Low-power reconfigurable acceleration of robust frequency-domain echo cancellation on FPGA

Tang, Wai-Chung; Ho, Chun Hok; Sham, Chiu-Wing; Yiu, Ka Fai Cedric

doi:10.1109/icgcs.2010.5543037

Cited by 3 publications

(1 citation statement)

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“…The resulting embedded system will find applications in modern multimedia systems. As a future extension, it would be of interest to investigate power consumption of the final design based on the technique in [30].…”

Section: Discussionmentioning

confidence: 99%

On a Real-Time Blind Signal Separation Noise Reduction System

Yiu

Low

2018

International Journal of Reconfigurable Computing

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Blind signal separation has been studied extensively in order to tackle the cocktail party problem. It explores spatial diversity of the received mixtures of sources by different sensors. By using the kurtosis measure, it is possible to select the source of interest out of a number of separated BSS outputs. Further noise cancellation can be achieved by adding an adaptive noise canceller (ANC) as postprocessing. However, the computation is rather intensive and an online implementation of the overall system is not straightforward. This paper intends to fill the gap by developing an FPGA hardware architecture to implement the system. Subband processing is explored and detailed functional operations are profiled carefully. The final proposed FPGA system is able to handle signals with sample rate over 20000 samples per second.

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Section: Discussionmentioning

confidence: 99%