Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

Xiang, Dong; Wen, Xiaoqing; Wang, Laung-Terng

doi:10.1109/tvlsi.2016.2606248

Cited by 58 publications

(26 citation statements)

References 52 publications

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“…Dong Xiang et al, [9] has proposed a pseudorandom generator based Test Pattern Generator (TPG) with weighted single test. The paper also explains Low Power (LP) deterministic BIST & reseeding.…”

Section: March Test Algorithmsmentioning

confidence: 99%

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Rayudu*,

‘G,

Rao

2019

IJRTE

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Memory testing and fault detection is an important phase in testing the hardware devices. This improves the overall performance of the system and prevents runtime failures in the devices. Built In Self Test (BIST) is a hardware memory test architecture deployed in many System on Chip devices to enable fault detection. This technique reduces the cost and time needed to test the memory systems. Different BIST modules need to be used to detect faults in different memories. As a result, design complexity increases. In order to overcome these above shortcomings, it is essential to develop advanced extensible Interface (AXI) with Block Random Access Memory (BRAM) and Design and Develop AXI based self-test memory architecture (March Algorithms) to achieve parallel read and write capability. The proposed model reduced the dynamic power and the clock cycles needed for simulation when compared to existing techniques

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Section: March Test Algorithmsmentioning

confidence: 99%

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Rayudu*,

‘G,

Rao

2019

IJRTE

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“…This programmable PRPG is having the capability of generating test patterns with desired toggling levels and improved fault coverage gradients. Later, scan-based low power BIST based WPSPG along with reseeding was proposed by Xiang et al supports both pseudorandom testing and deterministic BIST [15]. In the later case design-for-testability architecture can be slightly modified.…”

Section: A Background Literaturementioning

confidence: 99%

“…Such situations will increase test data volumes to keep the seeds in order. By adding small number of extra variables to LFSR or ring generator this problem can be solved easily [15].…”

Section: Proposed Ptpg Structurementioning

confidence: 99%

Low-Power Programmable Pseudorandom Test Pattern Generators with Test Compression Capabilities

2018

IJRTER

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-In this paper, a low-power programmable generator is proposed with a capability of producing required pseudorandom test patterns. The toggling levels and fault coverage gradients are adjustable in this work and are compared with the built-in self-test (BIST) based pseudorandom test pattern generators. To accomplish the objective of this paper a LFSR is tested with random variables and inputs and proved to be a better method as compared to the previous methods in the past. The proposed method could combine test compression with LBIST and both the systems could deliver high quality tests. Experimental results for the proposed design are reported herein with relevant outputs and expected outcomes.

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“…Another approach known as scan partitioning splits the scan chain into multiple partitions and activates only one partition at any time interval [3,[19][20][21][22][23][24][25]. The partitioning scheme in [19] limits the scan chain transitions from propagating to combinational logic during shifting by activating only one scan path at any time interval.…”

Section: Overview Of Hardware-based Test Power Reduction Approachesmentioning

confidence: 99%

“…A segment regrouping algorithm has been proposed by Yamato et al in [23] which identifies an optimal combination of scan segments to be clocked simultaneously and results in further instantaneous shift power reduction in the scan chain. Methods in [24,25] employ a scan chain grouping technique where only a single scan chain in each group is activated at any time during shift-in and shift-out cycles, and all other scan chains are disabled. Thus, repeated shift-in (shift-out) cycles are required to load the test data (or to shift-out the response data).…”

Section: Overview Of Hardware-based Test Power Reduction Approachesmentioning

confidence: 99%

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Naeini

Dass²,

Ooi

2017

JLPEA

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Abstract:Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology.

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Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding

Cited by 58 publications

References 52 publications

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Design and Development of A Modified AXI Based BIST Technique for Memory Architectures

Low-Power Programmable Pseudorandom Test Pattern Generators with Test Compression Capabilities

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

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