2009
DOI: 10.1109/tcad.2009.2030445
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Low-Power Scan Operation in Test Compression Environment

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Cited by 55 publications
(46 citation statements)
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“…In this case we used a single shadow register to favor the TDV measurements of this method. The shadow register was implemented using both techniques proposed in [30] and [46] (internal XOR tap or one additional ATE channel) and the best result is reported in every case. In the case of LPDR, the repeat command was utilized to further reduce the compressed test data.…”
Section: Resultsmentioning
confidence: 99%
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“…In this case we used a single shadow register to favor the TDV measurements of this method. The shadow register was implemented using both techniques proposed in [30] and [46] (internal XOR tap or one additional ATE channel) and the best result is reported in every case. In the case of LPDR, the repeat command was utilized to further reduce the compressed test data.…”
Section: Resultsmentioning
confidence: 99%
“…A few symbol-based TDC techniques, such as [7]- [10], [15], inherently offer low shift power but they are not suitable for cores with multiple scan chains. Recently, linear decompressors that offer a low switching activity during testing emerged [30]- [32]. These techniques require additional data to control the switching activity.…”
Section: T He Main Objective Of Test Data Compression (Tdc)mentioning
confidence: 99%
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“…Without additional DFT hardware, it is also inapplicable when the compression ratio is high. In [29], the low shift power decompressor was proposed by inserting a low shift power controller between decompressor outputs and scan chain inputs. Based on the observation that the majority of scan chains have no specified bit in each generated test cube, this method fills a large percentage of scan chains with constant 0.…”
Section: X-fill Strategiesmentioning
confidence: 99%
“…The hierarchical clock gaters make the test generator more effective to generate test patterns with lower capture power. The test generation procedures that utilize the clock gaters to reduce the capture power can be found in [29] and [31]. The main steps including those procedures are summarized as follows:…”
Section: Clock Gating Controlmentioning
confidence: 99%