With two-dimensional large-scale integrated circuits (ICs) approaching the limit of Moore's Law, the most promising solution is three-dimensional (3D) ICs based on chip stacking. 1 -3 The critical architectural element in 3D ICs is the vertical interconnect developed using through-Si via (TSV) and Cu microbump techniques. Thousands of microbumps are typically present on a given TSV chip. Pb-free solder has been employed for the microbumps to join two chips vertically. Overall, the solder joint is a very mature form of technology widely used in fl ip-chip technology, 4 in which solder bumps are fabricated on Si dies, and then the Si dies are fl ipped over to join with polymer substrates to form vertical interconnects.Figure 1 a presents a cross-sectional scanning electron microscope image of a typical fl ip-chip joint with Sn2.5Ag solder. 5 The joint is 100 μ m in diameter, and the solder is approximately 70 μ m in height. As labeled in the fi gure, the under-bump metallization (UBM) on the chip side is 5 μ m Cu/3 μ m Ni. On the substrate side, the metallization is 5 μ m electroless Ni on Cu traces. The solder has reacted with the metallization on the chip and substrate sides to form Ni 3 Sn 4 intermetallic compounds of 1.0 μ m thickness, such that the joint can provide electrical and thermal conduction, as well as mechanical strength to hold the chip and the substrate. The solder volume is estimated to be 6 × 10 5 μ m 3 , which is much larger than that of the UBM.As the microelectronic industry shifts to 3D ICs, more inputs/outputs are needed. Therefore, microbumps of 20-μ m diameter are currently being adopted to be the vertical interconnects between chips. The microbumps have been successfully fabricated by refl ow or thermo-compression. 6 -14 Typically, refl ow is carried out in an oven at a temperature above the melting point of the solder for approximately one minute, whereas thermo-compression is achieved by a bonder with a compressive force above the melting point for a few seconds. Figure 1b shows the structure of a typical Sn2.5Ag microbump with 5 μ m Cu/3 μ m Ni UBM on both top and bottom chips. The solder height decreases to only 6.2 μ m. Nevertheless, the thickness of the UBM cannot be scaled down accordingly due to consideration of metallurgical reactions. If the UBM is too thin, intermetallics (IMCs) would detach from the UBM when the UBM is consumed. 15 Therefore, the UBM thickness of the microbump remains approximately the same as that of the fl ip-chip joint. It is noteworthy that the transistor has gradually scaled down in the past three decades. For example, the minimum feature length shrank from 90 nm to 65 nm nodes With the electronics packaging industry shifting increasingly to three-dimensional packaging, microbumps have been adopted as the vertical interconnects between chips. Consequently, solder volumes have decreased dramatically, and the solder thickness has reduced to a range between a few and 10 microns. The solder volume of a microbump is approximately two orders of magnitude smalle...