Low-temperature growth of In-assisted silicon nanowires

Convertino, Annalisa; Cuscunà, Massimo; Nicotra, Giuseppe; Spinella, C.; Felisari, L.; Fortunato, G.; Martelli, F.

doi:10.1016/j.jcrysgro.2011.09.009

Cited by 18 publications

(20 citation statements)

References 21 publications

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“…The density can be of course increased by increasing the silane partial pressure, see figure 1(d), but the reached density is still not satisfactory. A further increase of the SiH 4 partial pressure would increase the deposition rate, which adversely affects the NW crystallinity and lead to a higher amount of parasitic growth [20,24]. We have instead used a pre-treatment of the Si/SiO 2 /polyimide/a-Si/Au substrate in H 2 plasma that has been shown to be useful to the NW growth at low temperatures [26].…”

Section: Resultsmentioning

confidence: 99%

Direct growth of Si nanowires on flexible organic substrates

et al. 2016

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The full-text may be used and/or reproduced, and given to third parties in any format or medium, without prior permission or charge, for personal research or study, educational, or not-for-prot purposes provided that:• a full bibliographic reference is made to the original source • a link is made to the metadata record in DRO • the full-text is not changed in any way The full-text must not be sold in any format or medium without the formal permission of the copyright holders.Please consult the full DRO policy for further details. Abstract A key characteristic of semiconductor nanowires (NWs) is that they grow on any substrate that stands up the growth conditions, paving the way for their use in flexible electronics. We report on the direct growth of crystalline silicon nanowires on polyimide substrates. The Si NWs are grown by plasma-enhanced chemical vapor deposition, which allows the growth to proceed at temperatures low enough to be compatible with plastic substrates (350 °C), where gold or indium are used as growth seeds. In is particularly interesting as the seed not only because it leads to a better NW crystal quality but also because it overcomes a core problem induced by the use of Au in silicon processing, i.e. Au creates deep carrier traps when incorporated in the nanowires.

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Section: Resultsmentioning

confidence: 99%

Direct growth of Si nanowires on flexible organic substrates

et al. 2016

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“…Indium nanoparticles could be elaborated by different techniques such as vapor deposition technique [14], electrochemical reduction [15], chemical reduction of salts [16], laser ablation [17], and reduction of indium-tin oxide or indium layers by hydrogen or helium plasma [18][19][20]. Iacopi et al have obtained indium particles with diameter range of 40-80 nm by electrodeposition on silicon substrate from an aqueous solution (InCl 3 , KCl, and HCl) [21].…”

Section: Introductionmentioning

confidence: 99%

Investigation of Indium Oxide Effect on Indium Particles Properties Used as Silicon Nanowires Catalyst

Zaghouani¹

2021

Post-Transition Metals

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In this chapter, we investigate on indium particles elaboration by different annealing processes: rapid thermal annealing (RTA) and conventional processes. The elaborated particles are dedicated to be used as catalyst for silicon nanowires' (SiNWs) growth by vapor-liquid-solid (VLS) process. The annealing parameters effect on indium particles properties is studied. After conventional annealing, the indium layer is cracked into elongated and inhomogeneous islands of micrometric sizes. XRD analysis depicts, in addition to pure indium planes, the presence of new peaks attributed to indium oxide (In 2 O 3) planes formed during annealing. After hydrogen treatment with a flow rate of 60 sccm during 10 min, some In 2 O 3 peaks are eliminated and replaced by new indium peaks, explaining the amelioration of indium particles morphology. These formed particles have been used as catalyst for SiNWs' growth. A low density of SiNWs is obtained, attributed to In 2 O 3 persistence, decreasing the indium catalytic effect. Quasi-spherical and homogeneously distributed indium particles with an average size of 422 nm are successfully grown in one step by the RTA process during short time (5 min) at lower temperature (450°C). XRD analysis shows the absence of indium oxide in the contrary to those formed by the conventional furnace. SiNWs with higher density are obtained, highlighting the harmful role of indium oxide.

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“…Although several growth techniques have been reported [ 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 ], silicon nanowires (Si NWs) fabrication is still quite complex and challenging. The vapour-liquid-solid (VLS) approach is the most commonly adopted technique for the synthesis of Si NWs through the aid of a metal (or metal alloy) seed catalyst that induce the wires formation upon Si precipitation when above the Me/Si alloy eutectic temperature [ 14 ].…”

Section: Introductionmentioning

confidence: 99%

“…Even though widely diffused, VLS presents several drawbacks, mainly (i) high process temperatures, (ii) formation of NWs bundles, (iii) poor control on the structural features and (iv) non-uniform doping which limit the real integration of VLS NWs in new devices. Moreover, the choice of the metal catalyst is crucial in order to determine the NWs properties and a large number of attempts have been reported in order to circumvent the detrimental effect of catalyst impurities incorporation into device [ 19 , 20 ]. Other top-down approaches such as lithography and reactive ion etching are also available, allowing the controlled synthesis of Si NWs with defined structural parameters [ 15 , 16 , 17 , 18 ].…”

Section: Introductionmentioning

confidence: 99%

Low Cost Fabrication of Si NWs/CuI Heterostructures

et al. 2018

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In this paper, we present the realization by a low cost approach compatible with silicon technology of new nanostructures, characterized by the presence of different materials, such as copper iodide (CuI) and silicon nanowires (Si NWs). Silicon is the principal material of the microelectronics field for its low cost, easy manufacturing and market stability. In particular, Si NWs emerged in the literature as the key materials for modern nanodevices. Copper iodide is a direct wide bandgap p-type semiconductor used for several applications as a transparent hole conducting layers for dye-sensitized solar cells, light emitting diodes and for environmental purification. We demonstrated the preparation of a solid system in which Si NWs are embedded in CuI material and the structural, electrical and optical characterization is presented. These new combined Si NWs/CuI systems have strong potentiality to obtain new nanostructures characterized by different doping, that is strategic for the possibility to realize p-n junction device. Moreover, the combination of these different materials opens the route to obtain multifunction devices characterized by promising absorption, light emission, and electrical conduction.

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Low-temperature growth of In-assisted silicon nanowires

Cited by 18 publications

References 21 publications

Direct growth of Si nanowires on flexible organic substrates

Direct growth of Si nanowires on flexible organic substrates

Investigation of Indium Oxide Effect on Indium Particles Properties Used as Silicon Nanowires Catalyst

Low Cost Fabrication of Si NWs/CuI Heterostructures

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