Low Temperature Pre-Epi Treatment: Critical Parameters to Control Interface Contamination

Abstract

Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

Deposition of O atomic layers on Si(100) substrates for epitaxial Si-O superlattices: investigation of the surface chemistry

“…The load ports are also maintained with inert N 2 ambient to protect the wafers from surface oxidation. Before the O deposition, an 850 • C pre-epi clean for 2 min is performed in H 2 at 40 Torr in the epsilon CVD reactor to remove the residual contaminations from the wet cleaning processes [28]. The wafers are cooled down to 350 • C in H 2 to leave the surface H terminated [29].…”

High Ge Content SiGe Selective Processes for Source/Drain in Manufacturing the Next Generations of pMOS Transistors

“…7 Since selective Si 0.55 Ge 0.45 and Si 0.25 Ge 0.75 processes are developed for use on either relaxed or strained Ge layers deposited in an active Si window (so called planar structure) or in a narrow trench (Fin FET structure), thermal budget must be kept low in order to avoid Ge reflow (see Fig. In this work all wafers (blanket Si and the wafers with oxide and nitride layers) were baked in H 2 at 1050 • C in order to remove native oxide.…”

Study of electrically active defects in epitaxial layers on silicon

“…A crucial step in silicon epitaxy is the preparation of a clean silicon surface prior to the deposition [1]. The removal of oxygen and carbon contamination is essential for a defect-free growth of good quality layers.…”