Low-temperature pre-treatments in a vertical epitaxial reactor with an improved vacuum load-lock chamber

Abstract

Low-temperature (<750 • C) surface preparation for epitaxial growth poses extra challenges for both hardware of a vertical batch epitaxial reactor and chemistry of in situ pre-epi treatments. The vacuum load-lock chamber of the vertical batch tool has been improved to ensure that residual moisture and oxygen concentrations are suppressed to less than 0.1 ppm. Si-based and Cl-based gases or a mixture of these gases are investigated in terms of effectiveness to remove interfacial residual oxygen at low temperatures (<750 • C). Under an optimized process condition, we found that interfacial oxygen can be reduced to less than 1 × 10 12 cm −2 levels by low-temperature treatment with a mixture of Si-based and Cl-based gases.

SiGe channel deposition by batch epitaxy

“…Subsequently, the wafers were loaded into a quartz boat within the vacuum load-lock chamber with a certain queue time to minimize re-oxidation. The in-situ clean in the furnace was either a low temperature pretreatment clearly below 750°C [6] or a conventional H 2 bake at or above 800°C followed by a low temperature SiGe deposition. Cross-sectional transmission electron microscope (XTEM) was carried out to study the growth morphology of different SiGe channels.…”

“…Since temperature ramping requires a long time in a thermally slow batch system the in-situ clean temperature should be close to the deposition temperature. So a low temperature pretreatment clearly below 750°C [6] has a large impact on throughput. Initial results indicated that a low temperature pretreatment has the same cleaning efficiency as a conventional H 2 bake at 800°C.…”

Highly manufacturable silicon vertical diode switches for new memories using selective epitaxial growth with batch-type equipment

“…Furthermore, the single-wafer process suffers from inferior productivity especially when the growth amount of SEG exceeds 100 nm at temperature lower than 700 • C. Reduced growth rate imposes low throughput and prolonged thermal budget. Few researchers have been interested in and reported about batch process for SEG in order to surmount the drawback [21][22][23][24]. As for the application to SEG diode switches in nextgeneration memories, which requires SEG height larger than 200 nm with low thermal budget, the batch SEG is considered as the most promising solution to guarantee mass productivity.…”